Datasheet > 74HCT7403D,112

74HCT7403D,112

更新时间： 2024-02-10 09:53:30

品牌	Logo	应用领域
恩智浦 - NXP		先进先出芯片
页数	文件大小	规格书
28页	118K
描述
74HC(T)7403 - 4-Bit x 64-word FIFO register; 3-state SOP 16-Pin

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技术参数
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74HCT7403D,112 技术参数

Source Url Status Check Date：	2013-10-15 00:00:00	生命周期：	Transferred
零件包装代码：	SOP	包装说明：	PLASTIC, SOT-162, SO-16
针数：	16	Reach Compliance Code：	unknown
风险等级：	5.8	Base Number Matches：	1

74HCT7403D,112 数据手册

Philips Semiconductors

Product speciﬁcation

4-Bit x 64-word FIFO register; 3-state

74HC/HCT7403

FEATURES

QUICK REFERENCE DATA

GND = 0 V; T_amb= 25 °C; t_r= t_f= 6 ns.

• Synchronous or asynchronous

operation

TYP.

SYMBOL

_PHL/t_PLH

f_max

PARAMETER

CONDITIONS

UNIT

• 3-state outputs

HC HCT

• 30 MHz (typical) shift-in and

shift-out rates

propagation delay SO, C_L= 15 pF;

SI to DIR and DOR

V_CC= 5 V

• Readily expandable in word and bit

dimensions

maximum clock

frequency

MHz

• Pinning arranged for easy board

layout: input pins directly opposite

output pins

C_I

input capacitance

3.5

C_PD

power dissipation

capacitance per

package

note 1

475

490

• Output capability: driver (8 mA)

• I_CCcategory: LSI.

Note

1. For HC the condition is V_I= GND to V_CC

APPLICATIONS

For HCT the condition is V_I= GND to V_CC−1.5 V.

• High-speed disc or tape controller

• Communications buffer.

ORDERING INFORMATION

PACKAGE

EXTENDED

TYPE NUMBER

GENERAL DESCRIPTION

PINS

PIN POSITION

MATERIAL

CODE

The 74HC/HCT7403 are high-speed

Si-gate CMOS devices. They are

specified in compliance with JEDEC

standard no.7A.

74HC/HCT7403N

74HC/HCT7403D

DIL

plastic

SOT38Z

SOT162

SO16L

The “7403” is an expandable, First-In

First-Out (FIFO) memory organized

as 64 words by 4 bits. A guaranteed

15 MHz data-rate makes it ideal for

high-speed applications. A higher

data-rate can be obtained in

applications where the status flags

are not used (burst-mode).

With separate controls for shift-in (SI)

and shift-out (SO), reading and

writing operations are completely

independent, allowing synchronous

and asynchronous data transfers.

Additional controls include a

master-reset input (MR), an output

enable input (OE) and flags. The

data-in-ready (DIR) and

data-out-ready (DOR) flags indicate

the status of the device.

September 1993

123 4 5 6 7...28

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