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74HCT573D PDF预览

74HCT573D

更新时间: 2024-01-07 13:12:55
品牌 Logo 应用领域
恩智浦 - NXP 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 65K
描述
Octal D-type transparent latch; 3-state

74HCT573D 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.06其他特性:BROADSIDE VERSION OF 373
系列:HCTJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):53 ns认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

74HCT573D 数据手册

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Philips Semiconductors  
Product specification  
Octal D-type transparent latch; 3-state  
74HC/HCT573  
DC CHARACTERISTICS FOR 74HCT  
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.  
Output capability: bus driver  
ICC category: MSI  
Note to HCT types  
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications.  
To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.  
INPUT  
UNIT LOAD COEFFICIENT  
Dn  
LE  
OE  
0.35  
0.65  
1.25  
AC CHARACTERISTICS FOR 74HCT  
GND = 0 V; tr = tf = 6 ns; CL = 50 pF  
Tamb (°C)  
TEST CONDITIONS  
74HCT  
SYMBOL PARAMETER  
UNIT  
VCC  
+25  
40 to +85 40 to +125  
WAVEFORMS  
(V)  
min. typ. max. min. max. min. max.  
tPHL/ tPLH propagation delay  
Dn to Qn  
20  
18  
17  
35  
35  
30  
44  
44  
38  
53  
53  
45  
ns  
ns  
ns  
4.5 Fig.6  
4.5 Fig.7  
4.5 Fig.8  
tPHL/ tPLH propagation delay  
LE to Qn  
t
PZH/ tPZL 3-state output enable  
time  
OE to Qn  
tPHZ/ tPLZ 3-state output disable  
18  
30  
12  
38  
15  
45  
18  
ns  
4.5 Fig.8  
time  
OE to Qn  
t
THL/ tTLH output transition time  
5
5
7
4
ns  
ns  
ns  
ns  
4.5 Fig.6  
4.5 Fig.7  
4.5 Fig.9  
4.5 Fig.9  
tW  
tsu  
th  
enable pulse width  
HIGH  
16  
13  
9
20  
16  
11  
24  
20  
14  
set-up time  
Dn to LE  
hold time  
Dn to LE  
December 1990  
6

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