5秒后页面跳转
74HCT573PW PDF预览

74HCT573PW

更新时间: 2024-11-24 11:10:31
品牌 Logo 应用领域
安世 - NEXPERIA 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 274K
描述
Octal D-type transparent latch; 3-stateProduction

74HCT573PW 数据手册

 浏览型号74HCT573PW的Datasheet PDF文件第2页浏览型号74HCT573PW的Datasheet PDF文件第3页浏览型号74HCT573PW的Datasheet PDF文件第4页浏览型号74HCT573PW的Datasheet PDF文件第5页浏览型号74HCT573PW的Datasheet PDF文件第6页浏览型号74HCT573PW的Datasheet PDF文件第7页 
74HC573; 74HCT573  
Octal D-type transparent latch; 3-state  
Rev. 8 — 10 September 2021  
Product data sheet  
1. General description  
The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device  
features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs  
enter the latches. In this condition the latches are transparent, a latch output will change each time  
its corresponding D-input changes. When LE is LOW the latches store the information that was  
present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE  
causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not  
affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting  
resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Wide supply voltage range from 2.0 to 6.0 V  
CMOS low power dissipation  
High noise immunity  
Input levels:  
For 74HC573: CMOS level  
For 74HCT573: TTL level  
Inputs and outputs on opposite sides of package allowing easy interface with microprocessors  
Useful as input or output port for microprocessors and microcomputers  
3-state non-inverting outputs for bus-oriented applications  
Common 3-state output enable input  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Complies with JEDEC standards:  
JESD8C (2.7 V to 3.6 V)  
JESD7A (2.0 V to 6.0 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74HC573D  
-40 °C to +125 °C  
-40 °C to +125 °C  
-40 °C to +125 °C  
SO20  
plastic small outline package; 20 leads;  
body width 7.5 mm  
SOT163-1  
74HCT573D  
74HC573PW  
74HCT573PW  
74HC573BQ  
74HCT573BQ  
TSSOP20  
plastic thin shrink small outline package; 20 leads;  
body width 4.4 mm  
SOT360-1  
SOT764-1  
DHVQFN20 plastic dual in-line compatible thermal enhanced  
very thin quad flat package; no leads; 20 terminals;  
body 2.5 × 4.5 × 0.85 mm  
 
 
 

74HCT573PW 替代型号

型号 品牌 替代类型 描述 数据表
74HCT573PW,118 NXP

类似代替

74HC(T)573 - Octal D-type transparent latch; 3-state TSSOP2 20-Pin
MM74HCT573MTCX FAIRCHILD

功能相似

Bus Driver, HCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 4.40 MM, MO-153AC, TSSOP
SN74HCT573PW TI

功能相似

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

与74HCT573PW相关器件

型号 品牌 获取价格 描述 数据表
74HCT573PW,112 NXP

获取价格

74HC(T)573 - Octal D-type transparent latch; 3-state TSSOP2 20-Pin
74HCT573PW,118 NXP

获取价格

74HC(T)573 - Octal D-type transparent latch; 3-state TSSOP2 20-Pin
74HCT573PW-Q100 NXP

获取价格

Octal D-type transparent latch; 3-state
74HCT573PW-Q100 NEXPERIA

获取价格

Octal D-type transparent latch; 3-stateProduction
74HCT573PW-T NXP

获取价格

HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-
74HCT573-Q100 NXP

获取价格

Octal D-type transparent latch; 3-state
74HCT574 NXP

获取价格

Octal D-type flip-flop; positive edge-trigger; 3-state
74HCT574D NXP

获取价格

Octal D-type flip-flop; positive edge-trigger; 3-state
74HCT574D NEXPERIA

获取价格

Octal D-type flip-flop; positive edge-trigger; 3-stateProduction
74HCT574D,653 NXP

获取价格

74HC(T)574 - Octal D-type flip-flop; positive edge-trigger; 3-state SOP 20-Pin