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Datasheet > 74HC40103D,652
74HC40103D,652 PDF预览

74HC40103D,652

更新时间： 2024-11-30 14:47:03
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
25页 123K
描述
74HC40103 - 8-bit synchronous binary down counter SOP 16-Pin

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74HC40103D,652 技术参数

是否Rohs认证：符合生命周期：Transferred
零件包装代码：SOP包装说明：3.90 MM, PLASTIC, MS-012, SOT-109-1, SO-16
针数：16Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：7.2Is Samacsys：N
其他特性：TCO OUTPUT; RESET TO MAX COUNT计数方向：DOWN
系列：HC/UHJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：9.9 mm
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：10000000 Hz
最大I（ol）：0.004 A工作模式：SYNCHRONOUS
湿度敏感等级：1位数：8
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：2/6 V传播延迟（tpd）：450 ns
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：Counters最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：NICKEL PALLADIUM GOLD
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
触发器类型：POSITIVE EDGE宽度：3.9 mm
最小 fmax：12 MHzBase Number Matches：1

74HC40103D,652 数据手册

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74HC40103  
8-bit synchronous binary down counter  
Rev. 03 — 12 November 2004  
Product data sheet  
1. General description  
The 74HC40103 is a high-speed Si-gate CMOS device and are pin compatible with the  
40103 of the 4000B series. The 74HC40103 is specified in compliance with JEDEC  
standard no. 7A.  
The 74HC40103 consists of an 8-bit synchronous down counter with a single output which  
is active when the internal count is zero. The 74HC40103 contains a single 8-bit binary  
counter and has control inputs for enabling or disabling the clock (CP), for clearing the  
counter to its maximum count and for presetting the counter either synchronously or  
asynchronously. All control inputs and the terminal count output (TC) are active-LOW  
logic.  
In normal operation, the counter is decremented by one count on each positive-going  
transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is  
HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is  
LOW, and remains LOW for one full clock period.  
When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7)  
is clocked into the counter on the next positive-going clock transition regardless of the  
state of TE. When the asynchronous preset enable input (PL) is LOW, data at the jam  
input (P0 to P7) is asynchronously forced into the counter regardless of the state of PE,  
TE, or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word.  
When the master reset input (MR) is LOW, the counter is asynchronously cleared to its  
maximum count (decimal 255) regardless of the state of any other input.  
If all control inputs except TE are HIGH at the time of zero count, the counters will jump to  
the maximum count, giving a counting sequence of 256 clock pulses long.  
The 74HC40103 may be cascaded using the TE input and the TC output, in either a  
synchronous or ripple mode.  
 
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74HC40103D,652 替代型号

型号 品牌 替代类型 描述 数据表
74HC40103D,653 NXP

完全替代

 74HC40103 - 8-bit synchronous binary down counter SOP 16-Pin

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