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74HC40103PW PDF预览

74HC40103PW

更新时间： 2024-12-01 11:14:39
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
23页 831K
描述
8-bit synchronous binary down counterProduction

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74HC40103PW 技术参数

是否Rohs认证：符合生命周期：Active
包装说明：TSSOP,Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.61
Is Samacsys：N其他特性：TCO OUTPUT; RESET TO MAX COUNT
计数方向：DOWN系列：HC/UH
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：5 mm负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER工作模式：SYNCHRONOUS
湿度敏感等级：1位数：8
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260传播延迟（tpd）：450 ns
座面最大高度：1.1 mm最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
触发器类型：POSITIVE EDGE宽度：4.4 mm
最小 fmax：12 MHzBase Number Matches：1

74HC40103PW 数据手册

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74HC40103  
8-bit synchronous binary down counter  
Rev. 5 — 21 April 2016  
Product data sheet  
1. General description  
The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enabling  
or disabling the clock (CP), for clearing the counter to its maximum count and for  
presetting the counter either synchronously or asynchronously. In normal operation, the  
counter is decremented by one count on each positive-going transition of the clock (CP).  
Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count  
output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for  
one full clock period. When the synchronous preset enable input (PE) is LOW, data at the  
jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition  
regardless of the state of TE. When the asynchronous preset enable input (PL) is LOW,  
data at the jam input (P0 to P7) is asynchronously forced into the counter regardless of  
the state of PE, TE, or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word.  
When the master reset input (MR) is LOW, the counter is asynchronously cleared to its  
maximum count (decimal 255) regardless of the state of any other input. If all control  
inputs except TE are HIGH at the time of zero count, the counters will jump to the  
maximum count, giving a counting sequence of 256 clock pulses long. Device may be  
cascaded using the TE input and the TC output, in either a synchronous or ripple mode.  
Inputs include clamp diodes. This enables the use of current limiting resistors to interface  
inputs to voltages in excess of VCC  
.
2. Features and benefits  
Cascadable  
Synchronous or asynchronous preset  
Low-power dissipation  
Complies with JEDEC standard no. 7A  
CMOS input levels  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from 40 C to +80 C and from 40 C to +125 C  
3. Applications  
Divide-by-n counters  
Programmable timers  
Interrupt timers  
Cycle/program counters.  
1234567...23

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74HC40103PW 替代型号

型号 品牌 替代类型 描述 数据表
74HC40103PW-T NXP

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