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74HC393D/T3 PDF预览

74HC393D/T3

更新时间: 2024-02-11 19:44:33
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
25页 137K
描述
IC HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT-108-1, SOP-14, Counter

74HC393D/T3 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.02计数方向:UP
系列:HC/UHJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
工作模式:ASYNCHRONOUS湿度敏感等级:1
位数:4功能数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):190 ns认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:NEGATIVE EDGE宽度:3.9 mm
最小 fmax:24 MHzBase Number Matches:1

74HC393D/T3 数据手册

 浏览型号74HC393D/T3的Datasheet PDF文件第2页浏览型号74HC393D/T3的Datasheet PDF文件第3页浏览型号74HC393D/T3的Datasheet PDF文件第4页浏览型号74HC393D/T3的Datasheet PDF文件第5页浏览型号74HC393D/T3的Datasheet PDF文件第6页浏览型号74HC393D/T3的Datasheet PDF文件第7页 
74HC393; 74HCT393  
Dual 4-bit binary ripple counter  
Rev. 03 — 6 September 2005  
Product data sheet  
1. General description  
The 74HC393; HCT393 is a high-speed Si-gate CMOS device and is pin compatible with  
Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard  
no. 7A.  
The 74HC393; 74HCT393 contains 4-bit binary ripple counters with separate clocks  
(1CP and 2 CP) and master reset (1MR and 2MR) inputs to each counter.  
The operation of each half of the 74HC393; 74HCT393 is the same as the 74HC93;  
74HCT93, except no external clock connections are required.  
The counters are triggered by a HIGH-to-LOW transition of the clock inputs.  
The counter outputs are internally connected to provide clock inputs to succeeding  
stages. The outputs of the ripple counter do not change synchronously and should not be  
used for high-speed address decoding.  
The master resets (1MR and 2MR) are active-HIGH asynchronous inputs to each 4-bit  
counter. A HIGH level on the nMR input overrides the clock and sets the outputs LOW.  
2. Features  
Two 4-bit binary counters with individual clocks  
Divide by any binary module up to 28 in one package  
Two master resets to clear each 4-bit counter individually  
3. Quick reference data  
Table 1:  
Quick reference data  
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.  
Symbol  
74HC393  
tPHL, tPLH  
Parameter  
Conditions  
Min  
Typ  
Max Unit  
propagation delay  
nCP to nQ0  
CL = 15 pF; VCC = 5 V  
-
-
-
-
12  
5
-
-
-
-
ns  
nQx to nQ(x+1)  
nMR to nQx  
ns  
11  
99  
ns  
fclk(max)  
maximum clock  
frequency  
CL = 15 pF; VCC = 5 V  
MHz  
Ci  
input capacitance  
-
-
3.5  
23  
-
-
pF  
pF  
[1] [2]  
CPD  
power dissipation  
capacitance (per gate)  

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