Datasheet > 74HC32N,652

74HC32N,652

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
17页	132K
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74HC32N

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74HC32N,652 数据手册

74HC32; 74HCT32

NXP Semiconductors

Quad 2-input OR gate

Table 7.

Dynamic characteristics

GND = 0 V; C_L= 50 pF; for load circuit see Figure 7.

Symbol Parameter

Conditions

25 C

40 C to +125 C Unit

Max Max

(85 C) (125 C)

Min

Typ

Max

74HCT32

[1]

t_pd

propagation delay nA, nB to nY; see Figure 6

V_CC= 4.5 V

V_CC= 5.0 V; C_L= 15 pF

[2]

[3]

t_t

transition time

power dissipation per package;

capacitance V_I= GND to V_CC 1.5 V

V_CC= 4.5 V; see Figure 6

C_PD

[1] t_pdis the same as t_PHLand t_PLH

[2] t_tis the same as t_THLand t_TLH

[3] C_PDis used to determine the dynamic power dissipation (P_Din W):

P_D= C_PD V_CC² f_i N +  (C_L V_CC² f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

 (C_L V_CC² f_o) = sum of outputs.

11. Waveforms

ꢃ

ꢎ

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ꢇꢈꢉꢊꢋꢌꢍꢋꢌ

ꢃ

ꢑ

ꢀꢁꢂ

ꢌ

ꢏꢆꢅ

ꢏꢅꢆ

ꢃ

ꢄꢅ

ꢈ

ꢃ

ꢑ

ꢃ

ꢒ

ꢃ

ꢄꢆ

ꢌ

ꢐꢆꢅ

ꢐꢅꢆ

ꢀꢀꢀꢁꢂꢂꢃꢂꢄꢅ

Measurement points are given in Table 9.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig 6. Input to output propagation delays

Table 8.

Type

Measurement points

Input

V_M

Output

V_M

V_X

V_Y

74HC32

0.5V_CC

1.3 V

0.5V_CC

1.3 V

0.1V_CC

0.9V_CC

74HCT32

74HC_HCT32

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 4 September 2012

7 of 17

1...4 5 678 9 10...17

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