Datasheet > 74HC259D-Q100

74HC259D-Q100

更新时间： 2023-09-03 20:28:30

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
17页	282K
描述
8-bit addressable latchProduction

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74HC259D-Q100 数据手册

74HC259-Q100; 74HCT259-Q100

8-bit addressable latch

Rev. 2 — 2 September 2020

Product data sheet

1. General description

The 74HC259-Q100; 74HCT259-Q100 is an 8-bit addressable latch. The device features four

modes of operation. In the addressable latch mode, data on the D input is written into the latch

addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed

latches will retain their previous states. In memory mode, all latches retain their previous states and

are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the

addressed output follows the D input and all other outputs are LOW. In the reset mode, all outputs

are forced LOW and unaffected by the data or address inputs. Inputs include clamp diodes. This

enables the use of current limiting resistors to interface inputs to voltages in excess of V_CC

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

Wide supply voltage range from 2.0 V to 6.0 V

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

Complies with JEDEC standards:

•

JESD8C (2.7 V to 3.6 V)

JESD7A (2.0 V to 6.0 V)

•

Combined demultiplexer and 8-bit latch

Serial-to-parallel capability

Output from each storage bit available

Random (addressable) data entry

Easily expandable

Common reset input

Useful as a 3-to-8 active HIGH decoder

Input levels:

•

For 74HC259-Q100: CMOS level

For 74HCT259-Q100: TTL level

•

ESD protection:

•

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

•

Multiple package options

DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of

solder joints

12 3 4 5 6 7...17

下载PDF

与74HC259D-Q100相关器件

型号	品牌	描述	获取价格	数据表
74HC259D-T	NXP	IC HC/UH SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16, 3.90 MM, PLASTIC, MS-01	获取价格
74HC259N	NXP	8-bit addressable latch	获取价格
74HC259NB	NXP	HC/UH SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP16	获取价格
74HC259N-B	PHILIPS	D Latch, 1-Func, 8-Bit, CMOS, PDIP16	获取价格
74HC259PW	NEXPERIA	8-bit addressable latchProduction	获取价格
74HC259PW	NXP	8-bit addressable latch	获取价格