Datasheet > 74HC259PW-Q100

74HC259PW-Q100

更新时间： 2024-02-29 05:10:09

品牌	Logo	应用领域
恩智浦 - NXP		锁存器
页数	文件大小	规格书
20页	261K
描述
8-bit addressable latch

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技术参数
数据手册

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74HC259PW-Q100 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.59
其他特性：	1:8 DMUX FOLLOWED BY LATCH	系列：	HC/UH
JESD-30 代码：	R-PDSO-G16	长度：	5 mm
逻辑集成电路类型：	D LATCH	湿度敏感等级：	1
位数：	1	功能数量：	1
端子数量：	16	最高工作温度：	125 °C
最低工作温度：	-40 °C	输出极性：	TRUE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	传播延迟（tpd）：	255 ns
筛选级别：	AEC-Q100	座面最大高度：	1.1 mm
最大供电电压 (Vsup)：	6 V	最小供电电压 (Vsup)：	2 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	AUTOMOTIVE
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
触发器类型：	LOW LEVEL	宽度：	4.4 mm
Base Number Matches：	1

74HC259PW-Q100 数据手册

74HC259-Q100; 74HCT259-Q100

8-bit addressable latch

Rev. 1 — 30 July 2012

Product data sheet

1. General description

The 74HC259-Q100; 74HCT259-Q100 are high-speed Si-gate CMOS devices and are pin

compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with

JEDEC standard No. 7A.

The 74HC259-Q100; 74HCT259-Q100 are high-speed 8-bit addressable latches

designed for general-purpose storage applications in digital systems. They are

multifunctional devices capable of storing single-line data in eight addressable latches and

providing a 3-to-8 decoder and multiplexer function with active HIGH outputs (Q0 to Q7).

They also incorporate an active LOW common reset (MR) for resetting all latches as well

as an active LOW enable input (LE).

The 74HC259-Q100; 74HCT259-Q100 has four modes of operation:

• Addressable latch mode, in this mode data on the data line (D) is written into the

addressed latch. The addressed latch follows the data input with all non-addressed

latches remaining in their previous states.

• Memory mode, in this mode all latches remain in their previous states and are

unaffected by the data or address inputs.

• Demultiplexing mode (or 3-to-8 decoding), in this mode the addressed output follows

the state of the data input (D) with all other outputs in the LOW state.

• Reset mode, in this mode all outputs are LOW and unaffected by the address inputs

(A0 to A2) and data input (D).

When operating the 74HC259-Q100; 74HCT259-Q100 as an address latch, changing

more than one address bit could impose a transient wrong address. Therefore, this should

only be done while in the Memory mode.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Combined demultiplexer and 8-bit latch

 Serial-to-parallel capability

 Output from each storage bit available

 Random (addressable) data entry

 Easily expandable

 Common reset input

12 3 4 5 6 7...20

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74HC259PW-T	NXP	IC HC/UH SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16, 4.40 MM, PLASTIC, MO-15	获取价格
74HC259-Q100	NXP	8-bit addressable latch	获取价格
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