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74HC240PW-Q100 PDF预览

74HC240PW-Q100

更新时间: 2024-11-22 11:10:27
品牌 Logo 应用领域
安世 - NEXPERIA 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
14页 251K
描述
Octal buffer/line driver; 3-state; invertingProduction

74HC240PW-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.57
系列:HC/UHJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
逻辑集成电路类型:BUS DRIVER湿度敏感等级:1
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):150 ns
筛选级别:AEC-Q100座面最大高度:1.1 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

74HC240PW-Q100 数据手册

 浏览型号74HC240PW-Q100的Datasheet PDF文件第2页浏览型号74HC240PW-Q100的Datasheet PDF文件第3页浏览型号74HC240PW-Q100的Datasheet PDF文件第4页浏览型号74HC240PW-Q100的Datasheet PDF文件第5页浏览型号74HC240PW-Q100的Datasheet PDF文件第6页浏览型号74HC240PW-Q100的Datasheet PDF文件第7页 
74HC240-Q100; 74HCT240-Q100  
Octal buffer/line driver; 3-state; inverting  
Rev. 2 — 15 July 2020  
Product data sheet  
1. General description  
The 74HC240-Q100; 74HCT240-Q100 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-Power Schottky TTL (LSTTL).  
The 74HC240-Q100; 74HCT240-Q100 is a dual octal inverting buffer/line driver with 3-state  
outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on  
nOE causes the outputs to assume a high impedance OFF-state.  
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100  
(Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
Wide supply voltage range from 2.0 V to 6.0 V  
CMOS low power dissipation  
High noise immunity  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Complies with JEDEC standards:  
JESD8C (2.7 V to 3.6 V)  
JESD7A (2.0 V to 6.0 V)  
Inverting 3-state outputs  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)  
Multiple package options  
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of  
solder joints  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74HC240D-Q100  
74HCT240D-Q100  
-40 °C to +125 °C  
SO20  
plastic small outline package; 20 leads;  
body width 7.5 mm  
SOT163-1  
74HC240PW-Q100 -40 °C to +125 °C  
74HCT240PW-Q100  
TSSOP20  
plastic thin shrink small outline package;  
20 leads; body width 4.4 mm  
SOT360-1  
SOT764-1  
74HC240BQ-Q100  
74HCT240BQ-Q100  
-40 °C to +125 °C  
DHVQFN20 plastic dual in-line compatible thermal  
enhanced very thin quad flat package; no leads;  
20 terminals; body 2.5 × 4.5 × 0.85 mm  
 
 
 

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