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74HC243 PDF预览

74HC243

更新时间: 2024-11-20 21:55:27
品牌 Logo 应用领域
恩智浦 - NXP 总线收发器
页数 文件大小 规格书
17页 90K
描述
Quad bus transceiver; 3-state

74HC243 数据手册

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74HC243  
Quad bus transceiver; 3-state  
Rev. 03 — 12 November 2004  
Product data sheet  
1. General description  
The 74HC243 is a high-speed Si-gate CMOS device and is pin compatible with low power  
Schottky TTL (LSTTL). The 74HC243 is specified in compliance with JEDEC  
standard no. 7A.  
The 74HC243 is a quad bus transceiver featuring non-inverting 3-state bus compatible  
outputs in both send and receive directions. The 74HC243 is designed for 4-line  
asynchronous 2-way data communications between data buses.  
The output enable inputs (OEA and OEB) can be used to isolate the buses.  
The 74HC243 is similar to the 74HC242 but has non-inverting (true) outputs.  
2. Features  
Non-inverting 3-state outputs  
2-way asynchronous data bus communication  
Low-power dissipation  
Complies with JEDEC standard no. 7A  
ESD protection:  
HBM EIA/JESD22-A114-B exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V.  
Multiple package options  
Specified from 40 °C to +80 °C and from 40 °C to +125 °C.  

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