Datasheet > 74FCT162511CTPAG8

74FCT162511CTPAG8

更新时间： 2024-11-27 07:33:35

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
10页	107K
描述
TSSOP-56, Reel

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IDT54/74FCT162511AT/CT

FASTCMOS16-BITREGISTERED/LATCHEDTRANSCEIVER

MILITARYANDINDUSTRIALTEMPERATURERANGES

FAST CMOS 16-BIT

IDT54/74FCT162511AT/CT

REGISTERED/LATCHED

TRANSCEIVER WITH PARITY

FEATURES:

DESCRIPTION:

• 0.5 MICRON CMOS Technology

The FCT162511T 16-bit registered/latched transceiver with parity is built

usingadvanceddualmetalCMOStechnology. This high-speed, low-power

transceivercombinesD-typelatchesandD-typeflip-flopstoallowdataflowin

transparent, latched, or clocked modes. The device has a parity generator/

checkerintheA-to-BdirectionandaparitycheckerintheB-to-Adirection. Error

checkingisdoneatthebytelevelwithseparateparitybitsforeachbyte. Separate

errorflagsexitsforeachdirectionwithasingleerrorflagindicatinganerrorfor

eitherbyteintheA-to-Bdirectionandaseconderrorflagindicatinganerrorfor

eitherbyteintheB-to-Adirection. Theparityerrorflagsareopendrainoutputs

whichcanbetiedtogetherand/ortiedwithflagsfromotherdevicestoformasingle

errorflagorinterrupt. The parityerrorflags are enabledbythe OExx control

pins allowing the designer to disable the error flag during combinational

transitions.

Thecontrolpins LEAB,CLKAB,andOEAB controloperationintheA-to-B

directionwhileLEBA,CLKBA,andOEBAcontroltheB-to-Adirection. GEN/

CHKisonlyfortheselectionofA-to-Boperation. TheB-to-Adirectionisalways

incheckingmode. TheODD/EVENselectiscommonbetweenthetwodirections.

Except for the ODD/EVEN control, independent operation can be achieved

betweenthetwodirectionsbyusingthecorrespondingcontrollines.

• Typical tsk(o) (Output Skew) < 250ps, clocked mode

• Low input and output leakage ≤1µA (max)

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 5V ±10%

• Balanced Output Drivers:

– ±24mA(industrial)

– ±16mA(military)

• Series current limiting resistors

• Generate/Check, Check/Check modes

• Open drain parity error allows wire-OR

• Available in the following packages:

– Industrial: SSOP, TSSOP

– Military: CERPACK

FUNCTIONALBLOCKDIAGRAM

LEAB

CLKAB

Data

OEAB

Parity, data

B0-15

PB1,2

Parity

Latch/

GEN/CHK

Byte

Parity

PERB

Generator/

Checker

A0-15

PA1,2

(Open Drain)

ODD/EVEN

LEBA

CLKBA

Parity, Data

Parity, data

Latch/

OEBA

Byte

Parity

Checking

PERA

(Open Drain)

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

MILITARY AND INDUSTRIAL TEMPERATURE RANGES

SEPTEMBER 2009

DSC-2916/4

12 3 4 5 6 7...10

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与74FCT162511CTPAG8相关器件

型号	品牌	获取价格	描述	数据表
74FCT162543ATPACT	TI	获取价格	16-Bit Latched Transceivers
74FCT162543CTPACT	TI	获取价格	16-Bit Latched Transceivers
74FCT162543CTPVCG4	TI	获取价格	16-Bit Registered Transceivers with 3-State Outputs 56-SSOP -40 to 85
74FCT162543CTPVCT	TI	获取价格	16-Bit Latched Transceivers
74FCT162543ETPACT	TI	获取价格	16-Bit Latched Transceivers
74FCT162543ETPVCT	TI	获取价格	16-Bit Latched Transceivers
74FCT162543TPVCTG4	TI	获取价格	16-Bit Registered Transceivers with 3-State Outputs 56-SSOP -40 to 85
74FCT162646ATPACT	TI	获取价格	16-Bit Registered Transceivers
74FCT162646ATPVCG4	TI	获取价格	16-Bit Registered Transceivers
74FCT162646ATPVCT	TI	获取价格	16-Bit Registered Transceivers

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