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74FCT162652CTPACT PDF预览

74FCT162652CTPACT

更新时间: 2024-11-25 22:49:51
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
10页 79K
描述
16-Bit Registered Transceivers

74FCT162652CTPACT 数据手册

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1CY74FCT162652T  
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT16652T  
CY74FCT162652T  
SCCS061 - July 1994 - Revised March 2000  
16-Bit Registered Transceivers  
Features  
Functional Description  
• FCT-E speed at 3.8 ns  
• Power-off disable outputs permits live insertion  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Typical output skew < 250 ps  
• ESD > 2000V  
These 16-bit, high-speed, low-power, registered transceivers  
that are organized as two independent 8-bit bus transceivers  
with three-state D-type registers and control circuitry arranged  
for multiplexed transmission of data directly from the input bus  
or from the internal storage registers. OEAB and OEBA control  
pins are provided to control the transceiver functions. SAB and  
SBA control pins are provided to select either real-time or  
stored data transfer.  
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)  
packages  
Data on the A or B data bus, or both, can be stored in the  
internal D flip-flops by LOW-to-HIGH transitions at the  
appropriate clock pins (CLKAB or CLKBA), regardless of the  
select or enable control pins. When SAB and SBA are in the  
real-time transfer mode, it is also possible to store data without  
using the internal D-type flip-flops by simultaneously enabling  
OEAB and OEBA. In this configuration, each output reinforces  
its input. Thus, when all other data sources to the two sets of  
bus lines are at high impedance, each set of bus lines will  
remain at its last state. The output buffers are designed with a  
power-off disable feature that allows live insertion of boards.  
• Industrial temperature range of 40˚C to +85˚C  
• VCC = 5V ± 10%  
CY74FCT16652T Features:  
• 64 mA sink current, 32 mA source current  
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,  
TA = 25˚C  
CY74FCT162652T Features:  
• Balanced 24 mA output drivers  
• Reduced system switching noise  
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,  
TA= 25˚C  
The CY74FCT16652T is ideally suited for driving  
high-capacitance loads and low-impedance backplanes.  
The CY74FCT162652T has 24-mA balanced output drivers  
with current-limiting resistors in the outputs. This reduces the  
need for external terminating resistors and provides for  
minimal undershoot and reduced ground bounce. The  
CY74FCT162652T is ideal for driving transmission lines.  
Logic Block Diagrams  
OEAB  
1
OEAB  
2
OEBA  
1
OEBA  
2
CLKBA  
1
1
CLKBA  
2
SBA  
2
SBA  
1
CLKAB  
CLKAB  
2
SAB  
2
SAB  
1
B REG  
D
B REG  
D
C
C
A
1
2
A
1
1
A REG  
A REG  
D
C
D
C
B
B
1
1
1
2
TO 7 OTHER CHANNELS  
FCT16652-1  
FCT16652-2  
TO 7 OTHER CHANNELS  
Copyright © 2000, Texas Instruments Incorporated  

74FCT162652CTPACT 替代型号

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FCT162652CTPACTG4 TI

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FCT162652CTPACTE4 TI

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