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74F74 PDF预览

74F74

更新时间: 2024-11-10 22:15:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
7页 77K
描述
Dual D-Type Positive Edge-Triggered Flip-Flop

74F74 数据手册

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April 1988  
Revised September 2000  
74F74  
Dual D-Type Positive Edge-Triggered Flip-Flop  
the outputs until the next rising edge of the Clock Pulse  
input.  
General Description  
The F74 is a dual D-type flip-flop with Direct Clear and Set  
inputs and complementary (Q, Q) outputs. Information at  
the input is transferred to the outputs on the positive edge  
of the clock pulse. Clock triggering occurs at a voltage level  
of the clock pulse and is not directly related to the transition  
time of the positive-going pulse. After the Clock Pulse input  
threshold voltage has been passed, the Data input is  
locked out and information present will not be transferred to  
Asynchronous Inputs:  
LOW input to SD sets Q to HIGH level  
LOW input to CD sets Q to LOW level  
Clear and Set are independent of clock  
Simultaneous LOW on CD and SD  
makes both Q and Q HIGH  
Ordering Code:  
Order Number Package Number  
Package Description  
74F74SC  
74F74SJ  
74F74PC  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 2000 Fairchild Semiconductor Corporation  
DS009469  
www.fairchildsemi.com  

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