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74F646BSCX PDF预览

74F646BSCX

更新时间: 2024-11-09 20:27:47
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
18页 284K
描述
F/FAST SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, 0.300 INCH, SOIC-24

74F646BSCX 技术参数

生命周期:Transferred包装说明:SOP,
Reach Compliance Code:unknown风险等级:5.63
其他特性:DIRECTION CONTROL; SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED OR REAL TIME DATA系列:F/FAST
JESD-30 代码:R-PDSO-G24长度:15.4 mm
负载电容(CL):50 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
位数:8功能数量:1
端口数量:2端子数量:24
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
最大电源电流(ICC):150 mA传播延迟(tpd):8 ns
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

74F646BSCX 数据手册

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December 1994  
54F/74F646 74F646B 54F/74F648  
#
#
Octal Transceiver/Register with TRI-STATE Outputs  
É
General Description  
Features  
Y
Independent registers for A and B buses  
These devices consist of bus transceiver circuits with TRI-  
STATE, D-type flip-flops, and control circuitry arranged for  
multiplexed transmission of data directly from the input bus  
or from the internal registers. Data on the A or B bus will be  
clocked into the registers as the appropriate clock pin goes  
to a high logic level. Control G and direction pins are provid-  
ed to control the transceiver function. In the transceiver  
mode, data present at the high impedance port may be  
stored in either the A or the B register or in both. The select  
controls can multiplex stored and real-time (transparent  
mode) data. The direction control determines which bus will  
receive data when the enable control G is Active LOW. In  
the isolation mode (control G HIGH), A data may be stored  
in the B register and/or B data may be stored in the A regis-  
ter.  
Y
Multiplexed real-time and stored data  
Y
’F648 has inverting data paths  
Y
’F646/’F646B have non-inverting data paths  
Y
’F646B is a faster version of the ’F646  
Y
TRI-STATE outputs  
Y
300 mil slim DIP  
Y
Guaranteed 4000V minimum ESD protection  
Package  
Number  
Commercial  
74F646SPC  
Military  
Package Description  
N24C  
J24F  
24-Lead (0.300 Wide) Molded Dual-In-Line  
×
54F646DM (Note 2)  
24-Lead (0.300 Wide) Ceramic Dual-In-Line  
×
74F646SC (Note 1)  
74F646MSA (Note 1)  
M24B  
MSA24  
W24C  
E28A  
N24C  
M24B  
N24C  
J24F  
24-Lead (0.300 Wide) Molded Small Outline, JEDEC  
×
24-Lead Molded Shrink Small Outline, EIAJ, Type II  
54F646FM (Note 2)  
54F646LM (Note 2)  
24-Lead Cerpack  
28-Lead Ceramic Leadless Chip Carrier, Type C  
74F646BSPC  
24-Lead (0.300 Wide) Molded Dual-In-Line  
×
74F646BSC (Note 1)  
74F648SPC  
24-Lead (0.300 Wide) Molded Small Outline, JEDEC  
×
24-Lead (0.300 Wide) Molded Dual-In-Line  
×
54F648SDM (Note 2)  
24-Lead (0.300 Wide) Ceramic Dual-In-Line  
×
74F648SC (Note 1)  
M24B  
W24C  
E28A  
24-Lead (0.300 Wide) Molded Small Outline, JEDEC  
×
54F648FM (Note 2)  
54F648LM (Note 2)  
24-Lead Cerpack  
24-Lead Ceramic Leadless Chip Carrier, Type C  
e
Note 1: Devices also available in 13 reel. Use suffix  
SCX.  
×
Note 2: Military grade device with environmental and burn-in processing. Use suffix  
e
DMQB, FMQB and LMQB.  
Logic Symbols  
’F646/’F646B  
’F648  
TL/F/9580–1  
TL/F/9580–7  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9580  
RRD-B30M75/Printed in U. S. A.  

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