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74F646BSDMSACQB

更新时间： 2024-11-05 04:01:03

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
6页	72K
描述
Octal Transceiver/Register with TRI-STATE Outputs

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数据手册

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74F646BSDMSACQB 数据手册

March 1988

Revised January 2004

74F646

Octal Transceiver/Register with 3-STATE Outputs

General Description

Features

These devices consist of bus transceiver circuits with

3-STATE, D-type flip-flops, and control circuitry arranged

for multiplexed transmission of data directly from the input

bus or from the internal registers. Data on the A or B bus

will be clocked into the registers as the appropriate clock

pin goes to a high logic level. Control G and direction pins

are provided to control the transceiver function. In the

transceiver mode, data present at the high impedance port

may be stored in either the A or the B register or in both.

The select controls can multiplex stored and real-time

(transparent mode) data. The direction control determines

which bus will receive data when the enable control G is

Active LOW. In the isolation mode (control G HIGH), A data

may be stored in the B register and/or B data may be

stored in the A register.

■ Independent registers for A and B buses

■ Multiplexed real-time and stored data

■ 74F646 has non-inverting data paths

■ 3-STATE outputs

■ 300 mil slim DIP

Ordering Code:

Order Number Package Number

Package Description

74F646SC

M24B

MSA24

N24C

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

24-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

74F646MSA

74F646SPC

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

DS009580

www.fairchildsemi.com

12 3 4 5 6

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