74F524SDC

更新时间： 2024-09-20 13:02:31

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		/
页数	文件大小	规格书
9页	77K
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74F524SDC 数据手册

April 1988

Revised August 1999

74F524

8-Bit Registered Comparator

General Description

Features

The 74F524 is an 8-bit bidirectional register with parallel

input and output plus serial input and output progressing

from LSB to MSB. All data inputs, serial and parallel, are

loaded by the rising edge of the input clock. The device

functions are controlled by two control lines (S₀, S₁) to exe-

■ 8-Bit bidirectional register with bus-oriented input-output

■ Independent serial input-output to register

■ Register bus comparator with “equal to”, “greater than”

and “less than” outputs

■ Cascadable in groups of eight bits

cute shift, load, hold and read out.

■ Open-collector comparator outputs for AND-wired

expansion

An 8-bit comparator examines the data stored in the regis-

ters and on the data bus. Three true-HIGH, open-collector

outputs representing “register equal to bus”, “register

greater than bus” and “register less than bus” are provided.

These outputs can be disabled to the OFF state by the use

of Status Enable (SE). A mode control has also been pro-

vided to allow twos complement as well as magnitude com-

pare. Linking inputs are provided for expansion to longer

words.

■ Twos complement or magnitude compare

Ordering Code:

Order Number Package Number

Package Description

74F524SC

74F524PC

M20B

N20A

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

DS009546

www.fairchildsemi.com

12 3 4 5 6 7...9

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