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74F524SDCQR PDF预览

74F524SDCQR

更新时间: 2024-11-08 13:01:27
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
9页 77K
描述
Magnitude Comparator, F/FAST Series, 8-Bit, True Output, TTL, CDIP20, SLIM, CERAMIC, DIP-20

74F524SDCQR 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.7其他特性:WITH ARITHMETIC COMPARISON; WITH MUXED COMPARATOR INPUT PORT
系列:F/FASTJESD-30 代码:R-CDIP-T20
逻辑集成电路类型:MAGNITUDE COMPARATOR位数:8
功能数量:1端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:OPEN-COLLECTOR输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
传播延迟(tpd):23 ns认证状态:Not Qualified
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子位置:DUAL
Base Number Matches:1

74F524SDCQR 数据手册

 浏览型号74F524SDCQR的Datasheet PDF文件第2页浏览型号74F524SDCQR的Datasheet PDF文件第3页浏览型号74F524SDCQR的Datasheet PDF文件第4页浏览型号74F524SDCQR的Datasheet PDF文件第5页浏览型号74F524SDCQR的Datasheet PDF文件第6页浏览型号74F524SDCQR的Datasheet PDF文件第7页 
April 1988  
Revised August 1999  
74F524  
8-Bit Registered Comparator  
General Description  
Features  
The 74F524 is an 8-bit bidirectional register with parallel  
input and output plus serial input and output progressing  
from LSB to MSB. All data inputs, serial and parallel, are  
loaded by the rising edge of the input clock. The device  
functions are controlled by two control lines (S0, S1) to exe-  
8-Bit bidirectional register with bus-oriented input-output  
Independent serial input-output to register  
Register bus comparator with “equal to”, “greater than”  
and “less than” outputs  
Cascadable in groups of eight bits  
cute shift, load, hold and read out.  
Open-collector comparator outputs for AND-wired  
expansion  
An 8-bit comparator examines the data stored in the regis-  
ters and on the data bus. Three true-HIGH, open-collector  
outputs representing “register equal to bus”, “register  
greater than bus” and “register less than bus” are provided.  
These outputs can be disabled to the OFF state by the use  
of Status Enable (SE). A mode control has also been pro-  
vided to allow twos complement as well as magnitude com-  
pare. Linking inputs are provided for expansion to longer  
words.  
Twos complement or magnitude compare  
Ordering Code:  
Order Number Package Number  
Package Description  
74F524SC  
74F524PC  
M20B  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS009546  
www.fairchildsemi.com  

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