Datasheet > 74F199

74F199

更新时间： 2024-09-16 22:53:15

品牌	Logo	应用领域
恩智浦 - NXP		移位寄存器
页数	文件大小	规格书
8页	70K
描述
8-bit parallel-access shift register

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数据手册

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74F199 数据手册

Philips Semiconductors FAST Products

Product specification

8-bit parallel-access shift register

74F199

FEATURES

PIN CONFIGURATION

• Buffered clock and control inputs

• Shift right and parallel load capability

• Fully synchronous data transfers

• J-K(D) inputs to first stage

• Clock enable for hold (do nothing) mode

• Asynchronous Master Reset

DESCRIPTION

The 74F199 is an 8-bit Parallel Access Shift Register and its

functional characteristics are indicated in the Logic Diagram and

Function Table. The device is useful in a variety of shifting, counting

and storage applications. It performs serial, parallel, serial-to-parallel,

or parallel–to-serial data transfers at very high speeds.

GND 12

SF00152

The 74F199 operates in two primary modes: shift right (Q0→Q1)

and parallel load, which are controlled by the state of the Parallel

Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J

and K inputs when the PE input is High, and is shifted one bit in the

direction Q0→Q1→Q2 following each Low-to-High clock transition.

TYPICAL

SUPPLY CURRENT

(TOTAL)

TYPE

TYPICAL f

MAX

74F199

95MHz

70mA

The J and K inputs provide the flexibility of the J-K type input for

special applications, and by tying the two together the simple D-type

input is made for general applications.

ORDERING INFORMATION

COMMERCIAL RANGE

The device appears as eight common clocked D flip-flops when the

PE input is Low. After the Low-to-High clock transition, data on the

parallel inputs (D0–D7) is transferred to the respective Q0–Q7

outputs.

DESCRIPTION

= 5V ±10%, T

= 0°C to +70°C

amb

24-pin plastic slim DIP

(300mil)

N74F199N

N74F199D

All parallel and serial data transfers are synchronous, occurring after

each Low-to-High clock transition. The 74F199 utilizes

edge-triggered, therefore there is no restriction on the activity of the

J, K, Dn, and PE inputs for logic operation, other than the setup and

hold time requirements.

24-pin plastic SOL

A Low on the Master Reset (MR) input overrides all other inputs and

clears the register asynchronously forcing all bit positions to a Low

state.

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

D0–D7

J, K

DESCRIPTION

74F (U.L.) HIGH/LOW

1.0/1.0

LOAD VALUE HIGH/LOW

20µA/0.6mA

Parallel data inputs

J and K inputs

1.0/1.0

20µA/0.6mA

Parallel Enable input

Clock Enable input

1.0/1.0

20µA/0.6mA

1.0/1.0

20µA/0.6mA

Clock Pulse inputs (Active rising edge)

Master Reset input (Active Low)

Data outputs

1.0/1.0

20µA/0.6mA

1.0/1.0

20µA/0.6mA

Q0–Q7

50/33

1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

June 15, 1988

853–0082 93568

12 3 4 5 6 7 8

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与74F199相关器件

型号	品牌	获取价格	描述	数据表
74F199D	YAGEO	获取价格	Parallel In Parallel Out, F/FAST Series, 8-Bit, Right Direction, True Output, TTL, PDSO24
74F199D-T	YAGEO	获取价格	Parallel In Parallel Out, F/FAST Series, 8-Bit, Right Direction, True Output, TTL, PDSO24
74F199N	YAGEO	获取价格	Parallel In Parallel Out, F/FAST Series, 8-Bit, Right Direction, True Output, TTL, PDIP24
74F20	NSC	获取价格	Dual 4-Input NAND Gate
74F20	NXP	获取价格	Dual 4-input NAND gate
74F20	FAIRCHILD	获取价格	Dual 4-Input NAND Gate
74F20D	YAGEO	获取价格	NAND Gate, F/FAST Series, 2-Func, 4-Input, TTL, PDSO14
74F20DC	FAIRCHILD	获取价格	NAND Gate, F/FAST Series, 2-Func, 4-Input, TTL, CDIP14, CERAMIC, DIP-14
74F20DCQM	FAIRCHILD	获取价格	NAND Gate, TTL, CDIP14,
74F20DCQR	FAIRCHILD	获取价格	NAND Gate, F/FAST Series, 2-Func, 4-Input, TTL, CDIP14, CERAMIC, DIP-14

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