Datasheet > 74CBTLV3257D

74CBTLV3257D

更新时间： 2024-12-01 11:12:35

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
21页	354K
描述
Quad 1-of-2 multiplexer/demultiplexerProduction

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74CBTLV3257D 数据手册

74CBTLV3257

Quad 1-of-2 multiplexer/demultiplexer

Rev. 8 — 21 March 2023

Product data sheet

1. General description

The 74CBTLV3257 provides a quad 1-of-2 high-speed multiplexer/demultiplexer with common

select (S) and output enable (OE) inputs. The low ON resistance of the switch allows inputs

to be connected to outputs without adding propagation delay or generating additional ground

bounce noise. When pin OE = LOW, one of the two switches is selected (low-impedance ON-state)

with pin S. When pin OE = HIGH, all switches are in the high-impedance OFF-state, independent

of pin S.

Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times

across the entire V_CCrange from 2.3 V to 3.6 V.

To ensure the high-impedance OFF-state during power-up or power-down, OE should be tied

to the V_CCthrough a pull-up resistor. The minimum value of the resistor is determined by the

current-sinking capability of the driver.

This device is fully specified for partial power-down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the damaging backflow current through the device when it is

powered down.

2. Features and benefits

•

Supply voltage range from 2.3 V to 3.6 V

•

High noise immunity

Complies with JEDEC standard:

•

JESD8-5 (2.3 V to 2.7 V)

JESD8-B/JESD36 (2.7 V to 3.6 V)

•

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

CDM AEC-Q100-011 revision B exceeds 1000 V

•

5 Ω switch connection between two ports

Rail to rail switching on data I/O ports

CMOS low power consumption

Latch-up performance exceeds 250 mA per JESD78B Class I level A

I_OFFcircuitry provides partial Power-down mode operation

Multiple package options

Specified from -40 °C to +85 °C and -40 °C to +125 °C

12 3 4 5 6 7...21

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