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74CBTLV3257DS,118 PDF预览

74CBTLV3257DS,118

更新时间: 2024-12-01 15:42:47
品牌 Logo 应用领域
恩智浦 - NXP PC光电二极管逻辑集成电路
页数 文件大小 规格书
19页 171K
描述
74CBTLV3257 - Quad 1-of-2 multiplexer/demultiplexer SSOP1 16-Pin

74CBTLV3257DS,118 技术参数

是否Rohs认证:符合生命周期:Transferred
零件包装代码:SSOP1包装说明:SSOP, SSOP16,.25
针数:16Reach Compliance Code:compliant
风险等级:5.74Is Samacsys:N
系列:CBTLV/3BJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:4.9 mm
逻辑集成电路类型:MULTIPLEXER AND DEMUX/DECODER湿度敏感等级:1
功能数量:4输入次数:1
输出次数:2端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
电源:2.5/3.3 V传播延迟(tpd):0.25 ns
认证状态:Not Qualified座面最大高度:1.73 mm
子类别:Other Logic ICs最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

74CBTLV3257DS,118 数据手册

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74CBTLV3257  
Quad 1-of-2 multiplexer/demultiplexer  
Rev. 4 — 16 December 2011  
Product data sheet  
1. General description  
The 74CBTLV3257 provides a quad 1-of-2 high-speed multiplexer/demultiplexer with  
common select (S) and output enable (OE) inputs. The low ON resistance of the switch  
allows inputs to be connected to outputs without adding propagation delay or generating  
additional ground bounce noise. When pin OE = LOW, one of the two switches is selected  
(low-impedance ON-state) with pin S. When pin OE = HIGH, all switches are in the  
high-impedance OFF-state, independent of pin S.  
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall  
times across the entire VCC range from 2.3 V to 3.6 V.  
To ensure the high-impedance OFF-state during power-up or power-down, OE should be  
tied to the VCC through a pull-up resistor. The minimum value of the resistor is determined  
by the current-sinking capability of the driver.  
This device is fully specified for partial power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
2. Features and benefits  
Supply voltage range from 2.3 V to 3.6 V  
High noise immunity  
Complies with JEDEC standard:  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CDM AEC-Q100-011 revision B exceeds 1000 V  
5 switch connection between two ports  
Rail to rail switching on data I/O ports  
CMOS low power consumption  
Latch-up performance exceeds 250 mA per JESD78B Class I level A  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
Specified from 40 C to +85 C and 40 C to +125 C  
 
 

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