Datasheet > 74AXP1T57

74AXP1T57

更新时间： 2024-12-02 01:03:19

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
24页	271K
描述
Dual supply configurable multiple function gate

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74AXP1T57 数据手册

74AXP1T57

Dual supply configurable multiple function gate

Rev. 5 — 3 July 2017

Product data sheet

1 General description

The 74AXP1T57 is a dual supply configurable multiple function gate with Schmitt-trigger

inputs. It features three inputs (A, B and C), an output (Y) and dual supply pins (V_CCIand

V_CCO). The inputs are referenced to V_CCIand the output is referenced to V_CCO. All inputs

can be connected directly to V_CCIor GND. V_CCIcan be supplied at any voltage between

0.7 V and 2.75 V and V_CCOcan be supplied at any voltage between 1.2 V and 5.5 V. This

feature allows voltage level translation. The 74AXP1T57 can be configured as any of the

following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer.

This device ensures very low static and dynamic power consumption across the entire

supply range and is fully specified for partial power down applications using I_OFF. The

I_OFFcircuitry disables the output, preventing the potentially damaging backflow current

through the device when it is powered down.

2 Features and benefits

• Wide supply voltage range:

– V_CCI: 0.7 V to 2.75 V

– V_CCO: 1.2 V to 5.5 V

• Low input capacitance; C_I= 0.6 pF (typical)

• Low output capacitance; C_O= 1.8 pF (typical)

• Low dynamic power consumption; C_PD= 0.6 pF at V_CCI= 1.2 V (typical)

• Low dynamic power consumption; C_PD= 7.1 pF at V_CCO= 3.3 V (typical)

• Low static power consumption; I_CCI= 0.5 μA (85 °C maximum)

• Low static power consumption; I_CCO= 1.8 μA (85 °C maximum)

• High noise immunity

• Complies with JEDEC standard:

– JESD8-12A.01 (1.1 V to 1.3 V; A, B, C inputs)

– JESD8-11A.01 (1.4 V to 1.6 V)

– JESD8-7A (1.65 V to 1.95 V)

– JESD8-5A.01 (2.3 V to 2.7 V)

– JESD8-C (2.7 V to 3.6 V; Y output)

– JESD12-6 (4.5 V to 5.5 V; Y output)

• ESD protection:

– HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV

– CDM JESD22-C101E exceeds 1000 V

• Latch-up performance exceeds 100 mA per JESD78D Class II

• Inputs accept voltages up to 2.75 V

• Low noise overshoot and undershoot < 10 % of V_CCO

• I_OFFcircuitry provides partial power-down mode operation

• Multiple package options

12 3 4 5 6 7...24

中文翻译

下载PDF

与74AXP1T57相关器件

型号	品牌	获取价格	描述	数据表
74AXP1T57DC	NEXPERIA	获取价格	Dual supply configurable multiple function gate
74AXP1T57DC-Q100	NEXPERIA	获取价格	Dual supply configurable multiple function gate
74AXP1T57GN	NEXPERIA	获取价格	Dual supply configurable multiple function gate
74AXP1T57GS	NEXPERIA	获取价格	Dual supply configurable multiple function gate
74AXP1T57GT	NEXPERIA	获取价格	Dual supply configurable multiple function gate
74AXP1T57GX	NEXPERIA	获取价格	Dual supply configurable multiple function gate
74AXP1T57-Q100	NEXPERIA	获取价格	Dual supply configurable multiple function gate
74AXP2G07	NEXPERIA	获取价格	Low-power dual buffer with open-drain output
74AXP2G07GM	NEXPERIA	获取价格	Low-power dual buffer with open-drain output
74AXP2G07GN	NEXPERIA	获取价格	Low-power dual buffer with open-drain output

与74AXP1T57相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

53
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

42
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

70
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

66

产品中心

服务支持

精选活动

关于我们

帮助中心

74AXP1T57

74AXP1T57 数据手册

与74AXP1T57相关器件

与74AXP1T57相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

74AXP1T57

74AXP1T57 数据手册

与74AXP1T57相关器件

与74AXP1T57相关文章

您还可以找

您在本页遇到什么问题？