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74AXP1T57GX PDF预览

74AXP1T57GX

更新时间: 2024-12-02 01:03:19
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
24页 271K
描述
Dual supply configurable multiple function gate

74AXP1T57GX 数据手册

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74AXP1T57  
Dual supply configurable multiple function gate  
Rev. 5 — 3 July 2017  
Product data sheet  
1 General description  
The 74AXP1T57 is a dual supply configurable multiple function gate with Schmitt-trigger  
inputs. It features three inputs (A, B and C), an output (Y) and dual supply pins (VCCI and  
VCCO). The inputs are referenced to VCCI and the output is referenced to VCCO. All inputs  
can be connected directly to VCCI or GND. VCCI can be supplied at any voltage between  
0.7 V and 2.75 V and VCCO can be supplied at any voltage between 1.2 V and 5.5 V. This  
feature allows voltage level translation. The 74AXP1T57 can be configured as any of the  
following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer.  
This device ensures very low static and dynamic power consumption across the entire  
supply range and is fully specified for partial power down applications using IOFF. The  
IOFF circuitry disables the output, preventing the potentially damaging backflow current  
through the device when it is powered down.  
2 Features and benefits  
Wide supply voltage range:  
VCCI: 0.7 V to 2.75 V  
VCCO: 1.2 V to 5.5 V  
Low input capacitance; CI = 0.6 pF (typical)  
Low output capacitance; CO = 1.8 pF (typical)  
Low dynamic power consumption; CPD = 0.6 pF at VCCI = 1.2 V (typical)  
Low dynamic power consumption; CPD = 7.1 pF at VCCO = 3.3 V (typical)  
Low static power consumption; ICCI = 0.5 μA (85 °C maximum)  
Low static power consumption; ICCO = 1.8 μA (85 °C maximum)  
High noise immunity  
Complies with JEDEC standard:  
JESD8-12A.01 (1.1 V to 1.3 V; A, B, C inputs)  
JESD8-11A.01 (1.4 V to 1.6 V)  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A.01 (2.3 V to 2.7 V)  
JESD8-C (2.7 V to 3.6 V; Y output)  
JESD12-6 (4.5 V to 5.5 V; Y output)  
ESD protection:  
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV  
CDM JESD22-C101E exceeds 1000 V  
Latch-up performance exceeds 100 mA per JESD78D Class II  
Inputs accept voltages up to 2.75 V  
Low noise overshoot and undershoot < 10 % of VCCO  
IOFF circuitry provides partial power-down mode operation  
Multiple package options  
 
 

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