Datasheet > 74AUP2G132GS

74AUP2G132GS

更新时间： 2024-11-17 11:10:51

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
21页	305K
描述
Low-power dual 2-input NAND Schmitt triggerProduction

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74AUP2G132GS 数据手册

74AUP2G132

Low-power dual 2-input NAND Schmitt trigger

Rev. 10 — 23 January 2023

Product data sheet

1. General description

The 74AUP2G132 is a dual 2-input NAND gate with Schmitt-trigger inputs. This device ensures

very low static and dynamic power consumption across the entire V_CCrange from 0.8 V to 3.6 V.

This device is fully specified for partial power down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the potentially damaging backflow current through the device when

it is powered down.

2. Features and benefits

•

Wide supply voltage range from 0.8 V to 3.6 V

•

CMOS low power dissipation

High noise immunity

Low static power consumption; I_CC= 0.9 μA (maximum)

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

Overvoltage tolerant inputs to 3.6 V

Low noise overshoot and undershoot < 10 % of V_CC

I_OFFcircuitry provides partial Power-down mode operation

Complies with JEDEC standards:

•

JESD8-12 (0.8 V to 1.3 V)

JESD8-11 (0.9 V to 1.65 V)

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

•

ESD protection:

•

HBM JESD22-A114F Class 3A exceeds 5000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101E exceeds 1000 V

•

Multiple package options

Specified from -40 °C to +85 °C and -40 °C to +125 °C

3. Applications

•

Wave and pulse shaper

Astable multivibrator

Monostable multivibrator

12 3 4 5 6 7...21

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