Datasheet > 74AUP1T14GW

74AUP1T14GW

更新时间： 2023-09-03 20:29:30

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
14页	229K
描述
Low-power inverter with voltage-level translatorProduction

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74AUP1T14GW 数据手册

Nexperia

74AUP1T14

Low-power inverter with voltage-level translator

13. Abbreviations

Table 11. Abbreviations

Acronym

CDM

Description

Charged Device Model

CMOS

DUT

Complementary Metal-Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

14. Revision history

Table 12. Revision history

Document ID

74AUP1T14 v.3

Modifications:

Release date

Data sheet status

Change notice

Supersedes

20220125

Product data sheet

74AUP1T14 v.2

•

Fig. 8: Package outline drawing for SOT353-1 (TSSOP5) has changed.

74AUP1T14 v.2

Modifications:

20210719 Product data sheet 74AUP1T14 v.1

•

SOT1226 (X2SON5) package changed to SOT1226-3 (X2SON5) package.

Table 5: Derating values for P_tottotal power dissipation updated.

74AUP1T14 v.1

20171128

Product data sheet

74AUP1T14

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 25 January 2022

12 / 14

1...9 10 111213 14

中文翻译

下载PDF

与74AUP1T14GW相关器件

型号	品牌	获取价格	描述	数据表
74AUP1T14GX	NEXPERIA	获取价格	Low-power inverter with voltage-level translatorProduction
74AUP1T17GW	NEXPERIA	获取价格	Low-power buffer with voltage-level translatorProduction
74AUP1T17GX	NEXPERIA	获取价格	Low-power buffer with voltage-level translatorProduction
74AUP1T32	NEXPERIA	获取价格	Low-power 2-input OR-gate with voltage-level translator
74AUP1T32GW	NEXPERIA	获取价格	Low-power 2-input OR-gate with voltage-level translator
74AUP1T32GX	NEXPERIA	获取价格	Low-power 2-input OR-gate with voltage-level translator
74AUP1T34	NXP	获取价格	Low-power dual supply translating buffer
74AUP1T34	DIODES	获取价格	Single Bit Dual Power Supply Translating Buffer with 3 State Outputs
74AUP1T34GF	NXP	获取价格	Low-power dual supply translating buffer
74AUP1T34GM	NXP	获取价格	Low-power dual supply translating buffer