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74AUP1GU04GW PDF预览

74AUP1GU04GW

更新时间: 2023-09-03 20:31:08
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
18页 276K
描述
Low-power unbuffered inverterProduction

74AUP1GU04GW 数据手册

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Nexperia  
74AUP1GU04  
Low-power unbuffered inverter  
V
V
EXT  
CC  
5 kΩ  
V
I
V
O
G
DUT  
R
T
C
L
R
L
001aac521  
Test data is given in Table 10.  
Definitions for test circuit:  
RL = Load resistance;  
CL = Load capacitance including jig and probe capacitance;  
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator;  
VEXT = External voltage for measuring switching times.  
Fig. 5. Test circuit for measuring switching times  
Table 10. Test data  
Supply voltage  
VCC  
Load  
CL  
VEXT  
RL [1]  
tPLH, tPHL  
open  
tPZH, tPHZ  
tPZL, tPLZ  
0.8 V to 3.6 V  
5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ  
GND  
2 × VCC  
[1] For measuring enable and disable times RL = 5 kΩ.  
For measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ.  
12. Additional characteristics  
001aad074  
30  
g
fs  
(mA/V)  
R
bias  
= 560 kΩ  
20  
V
CC  
0.47 µF  
100 µF  
input  
output  
10  
V
I
A
I
O
(f = 1 kHz)  
GND  
mna050  
0
0
1
2
3
4
V
(V)  
CC  
VO is constant.  
Tamb = 25 °C.  
Fig. 6. Test set-up for measuring forward  
transconductance  
Fig. 7. Typical forward transconductance as a function  
of supply voltage  
©
74AUP1GU04  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 8 — 2 November 2022  
9 / 18  
 
 
 
 

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