Datasheet > 74AUP1T00GX

74AUP1T00GX

更新时间： 2024-01-31 02:49:28

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
15页	202K
描述
Low-power 2-input NAND gate with voltage-level translator

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74AUP1T00GX 数据手册

74AUP1T00

Low-power 2-input NAND gate with voltage-level translator

Rev. 1 — 23 November 2017

Product data sheet

1 General description

The 74AUP1T00 provides the single 2-input NAND function. This device ensures a

very low static and dynamic power consumption across the entire V_CCrange from

2.3 V to 3.6 V.

The 74AUP1T00 is designed for logic-level translation applications with input switching

levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single

2.5 V or 3.3 V supply voltage.

The wide supply voltage range ensures normal operation as battery voltage drops from

3.6 V to 2.3 V.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing the damaging backflow current through the

device when it is powered down.

Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across

the entire V_CCrange.

2 Features and benefits

• Wide supply voltage range from 2.3 V to 3.6 V

• High noise immunity

• ESD protection:

– HBM JESD22-A114F Class 3A exceeds 5000 V

– CDM JESD22-C101E exceeds 1000 V

• Low static power consumption; I_CC= 1.5 μA (maximum)

• Latch-up performance exceeds 100 mA per JESD 78 Class II

• Inputs accept voltages up to 3.6 V

• Low noise overshoot and undershoot < 10 % of V_CC

• I_OFFcircuitry provides partial power-down mode operation

• Multiple package options

• Specified from -40 °C to +85 °C and -40 °C to +125 °C

12 3 4 5 6 7...15

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