74AUP1G57GF

更新时间： 2024-01-19 05:32:46

品牌	Logo	应用领域
恩智浦 - NXP		逻辑集成电路光电二极管
页数	文件大小	规格书
22页	82K
描述
Low-power configurable multiple function gate

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74AUP1G57GF 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	HVBCC,	Reach Compliance Code：	compliant
风险等级：	1.52	系列：	AUP/ULP/V
JESD-30 代码：	R-PBCC-B6	长度：	1 mm
逻辑集成电路类型：	LOGIC CIRCUIT	功能数量：	1
端子数量：	6	最高工作温度：	125 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	HVBCC	封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	NOT SPECIFIED
座面最大高度：	0.35 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	0.8 V	标称供电电压 (Vsup)：	1.1 V
表面贴装：	YES	技术：	CMOS
温度等级：	AUTOMOTIVE	端子形式：	BUTT
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	0.8 mm	Base Number Matches：	1

74AUP1G57

Low-power conﬁgurable multiple function gate

Rev. 01. — 16 January 2006

Preliminary data sheet

1. General description

The 74AUP1G57 is a high-performance, low-power, low-voltage, Si-gate CMOS device,

superior to most advanced CMOS compatible TTL families.

This device ensures a very low static and dynamic power consumption across the entire

V_CCrange from 0.8 V to 3.6 V.

This device is fully speciﬁed for partial Power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backﬂow current through

the device when it is powered down.

The 74AUP1G57 provides conﬁgurable multiple functions. The output state is determined

by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,

NOR, XNOR, inverter and buffer. All inputs can be connected to V_CCor GND.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V_CCrange from 0.8 V to 3.6 V.

The inputs switch at different points for positive and negative-going signals. The difference

between the positive voltage V_T+and the negative voltage V_T−is deﬁned as the input

hysteresis voltage V_H.

2. Features

■ Wide supply voltage range from 0.8 V to 3.6 V

■ High noise immunity

■ ESD protection:

◆ HBM JESD22-A114-C Class 3A. Exceeds 5000 V

◆ MM JESD22-A115-A exceeds 200 V

◆ CDM JESD22-C101-C exceeds 1000 V

■ Low static power consumption; I_CC= 0.9 µA (maximum)

■ Latch-up performance exceeds 100 mA per JESD 78 Class II

■ Inputs accept voltages up to 3.6 V

■ Low noise overshoot and undershoot < 10 % of V_CC

■ I_OFFcircuitry provides partial Power-down mode operation

■ Multiple package options

■ Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

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