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74AUP1G32GM-Q100 PDF预览

74AUP1G32GM-Q100

更新时间: 2024-02-02 19:42:17
品牌 Logo 应用领域
安世 - NEXPERIA 逻辑集成电路
页数 文件大小 规格书
14页 227K
描述
Low-power 2-input OR-gate

74AUP1G32GM-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:unknown风险等级:5.59
JESD-609代码:e4逻辑集成电路类型:OR GATE
湿度敏感等级:1端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
Base Number Matches:1

74AUP1G32GM-Q100 数据手册

 浏览型号74AUP1G32GM-Q100的Datasheet PDF文件第4页浏览型号74AUP1G32GM-Q100的Datasheet PDF文件第5页浏览型号74AUP1G32GM-Q100的Datasheet PDF文件第6页浏览型号74AUP1G32GM-Q100的Datasheet PDF文件第8页浏览型号74AUP1G32GM-Q100的Datasheet PDF文件第9页浏览型号74AUP1G32GM-Q100的Datasheet PDF文件第10页 
Nexperia  
74AUP1G32-Q100  
Low-power 2-input OR-gate  
Symbol Parameter  
Conditions  
Min  
Typ [1]  
Max  
Unit  
Tamb = 25 °C; CL = 10 pF  
tpd  
propagation delay  
A, B to Y; see Fig. 7  
VCC = 0.8 V  
[2]  
[2]  
[2]  
[3]  
-
20.3  
5.9  
4.2  
3.5  
2.9  
2.7  
-
ns  
ns  
ns  
ns  
ns  
ns  
VCC = 1.1 V to 1.3 V  
VCC = 1.4 V to 1.6 V  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
2.3  
1.9  
1.7  
1.4  
1.3  
12.7  
7.7  
6.0  
4.6  
4.3  
Tamb = 25 °C; CL = 15 pF  
tpd propagation delay  
A, B to Y; see Fig. 7  
VCC = 0.8 V  
-
23.8  
6.7  
4.8  
4.0  
3.3  
3.1  
-
ns  
ns  
ns  
ns  
ns  
ns  
VCC = 1.1 V to 1.3 V  
VCC = 1.4 V to 1.6 V  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
3.3  
2.3  
2.0  
1.7  
1.5  
14.3  
8.6  
6.7  
5.3  
4.9  
Tamb = 25 °C; CL = 30 pF  
tpd propagation delay  
A, B to Y; see Fig. 7  
VCC = 0.8 V  
-
34.1  
9.0  
6.3  
5.3  
4.4  
4.2  
-
ns  
ns  
ns  
ns  
ns  
ns  
VCC = 1.1 V to 1.3 V  
VCC = 1.4 V to 1.6 V  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
4.5  
3.4  
2.6  
2.3  
2.2  
19.1  
11.3  
8.9  
7.0  
6.4  
Tamb = 25 °C  
CPD power dissipation  
capacitance  
f = 1 MHz; VI = GND to VCC  
VCC = 0.8 V  
-
-
-
-
-
-
2.5  
2.6  
2.8  
2.9  
3.4  
3.9  
-
-
-
-
-
-
pF  
pF  
pF  
pF  
pF  
pF  
VCC = 1.1 V to 1.3 V  
VCC = 1.4 V to 1.6 V  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
[1] All typical values are measured at nominal VCC  
.
[2] tpd is the same as tPLH and tPHL  
.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).  
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
Σ(CL × VCC2 × fo) = sum of the outputs.  
©
74AUP1G32_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2019. All rights reserved  
Product data sheet  
Rev. 3 — 28 January 2019  
7 / 14  
 

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