5秒后页面跳转
74AUP1G32GM-Q100 PDF预览

74AUP1G32GM-Q100

更新时间: 2024-02-23 02:19:23
品牌 Logo 应用领域
安世 - NEXPERIA 逻辑集成电路
页数 文件大小 规格书
14页 227K
描述
Low-power 2-input OR-gate

74AUP1G32GM-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:unknown风险等级:5.59
JESD-609代码:e4逻辑集成电路类型:OR GATE
湿度敏感等级:1端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
Base Number Matches:1

74AUP1G32GM-Q100 数据手册

 浏览型号74AUP1G32GM-Q100的Datasheet PDF文件第1页浏览型号74AUP1G32GM-Q100的Datasheet PDF文件第2页浏览型号74AUP1G32GM-Q100的Datasheet PDF文件第3页浏览型号74AUP1G32GM-Q100的Datasheet PDF文件第5页浏览型号74AUP1G32GM-Q100的Datasheet PDF文件第6页浏览型号74AUP1G32GM-Q100的Datasheet PDF文件第7页 
Nexperia  
74AUP1G32-Q100  
Low-power 2-input OR-gate  
10. Static characteristics  
Table 7. Static characteristics  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Tamb = 25 °C  
Conditions  
Min  
Typ  
Max  
Unit  
VIH  
HIGH-level input  
voltage  
VCC = 0.8 V  
0.70 × VCC  
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
0.65 × VCC  
-
1.6  
-
VCC = 3.0 V to 3.6 V  
2.0  
-
VIL  
LOW-level input  
voltage  
VCC = 0.8 V  
-
-
-
-
0.30 × VCC  
0.35 × VCC  
0.7  
VCC = 0.9 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
0.9  
VOH  
HIGH-level output  
voltage  
VI = VIH or VIL  
IO = -20 μA; VCC = 0.8 V to 3.6 V  
IO = -1.1 mA; VCC = 1.1 V  
IO = -1.7 mA; VCC = 1.4 V  
IO = -1.9 mA; VCC = 1.65 V  
IO = -2.3 mA; VCC = 2.3 V  
IO = -3.1 mA; VCC = 2.3 V  
IO = -2.7 mA; VCC = 3.0 V  
IO = -4.0 mA; VCC = 3.0 V  
VI = VIH or VIL  
VCC - 0.1  
0.75 × VCC  
1.11  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.32  
2.05  
1.9  
2.72  
2.6  
VOL  
LOW-level output  
voltage  
IO = 20 μA; VCC = 0.8 V to 3.6 V  
IO = 1.1 mA; VCC = 1.1 V  
IO = 1.7 mA; VCC = 1.4 V  
IO = 1.9 mA; VCC = 1.65 V  
IO = 2.3 mA; VCC = 2.3 V  
IO = 3.1 mA; VCC = 2.3 V  
IO = 2.7 mA; VCC = 3.0 V  
IO = 4.0 mA; VCC = 3.0 V  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1  
0.3 × VCC  
0.31  
V
V
V
0.31  
V
0.31  
V
0.44  
V
0.31  
V
0.44  
V
II  
input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V  
±0.1  
μA  
μA  
IOFF  
power-off leakage  
current  
VI or VO = 0 V to 3.6 V; VCC = 0 V  
±0.2  
ΔIOFF  
ICC  
additional power-off  
leakage current  
VI or VO = 0 V to 3.6 V;  
VCC = 0 V to 0.2 V  
-
-
-
-
-
-
±0.2  
0.5  
40  
μA  
μA  
μA  
supply current  
VI = GND or VCC; IO = 0 A;  
VCC = 0.8 V to 3.6 V  
ΔICC  
additional supply  
current  
VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V [1]  
CI  
input capacitance  
output capacitance  
VCC = 0 V to 3.6 V; VI = GND or VCC  
VO = GND; VCC = 0 V  
-
-
0.8  
1.7  
-
-
pF  
pF  
CO  
©
74AUP1G32_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2019. All rights reserved  
Product data sheet  
Rev. 3 — 28 January 2019  
4 / 14  
 

与74AUP1G32GM-Q100相关器件

型号 品牌 描述 获取价格 数据表
74AUP1G32GN NXP Low-power 2-input OR-gate

获取价格

74AUP1G32GN NEXPERIA Low-power 2-input OR-gateProduction

获取价格

74AUP1G32GS NXP Low-power 2-input OR-gate

获取价格

74AUP1G32GS NEXPERIA Low-power 2-input OR-gateProduction

获取价格

74AUP1G32GS,132 NXP 74AUP1G32 - Low-power 2-input OR-gate

获取价格

74AUP1G32GW NXP Low-power 2-input OR gate

获取价格