5秒后页面跳转
74AUP1G132GM PDF预览

74AUP1G132GM

更新时间: 2024-01-04 12:53:38
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
19页 285K
描述
Low-power 2-input NAND Schmitt triggerProduction

74AUP1G132GM 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否无铅: 不含铅
是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SON包装说明:1 X 1.45 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-886, SON-6
针数:6Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.35
系列:AUP/ULP/VJESD-30 代码:R-PDSO-N6
JESD-609代码:e3长度:1.45 mm
负载电容(CL):30 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.0017 A湿度敏感等级:1
功能数量:1输入次数:2
端子数量:6最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:VSON封装等效代码:SOLCC6,.04,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:1.2/3.3 V
Prop。Delay @ Nom-Sup:27.9 ns传播延迟(tpd):27.9 ns
认证状态:Not Qualified施密特触发器:YES
座面最大高度:0.5 mm子类别:Gates
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.8 V
标称供电电压 (Vsup):1.1 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:1 mm
Base Number Matches:1

74AUP1G132GM 数据手册

 浏览型号74AUP1G132GM的Datasheet PDF文件第13页浏览型号74AUP1G132GM的Datasheet PDF文件第14页浏览型号74AUP1G132GM的Datasheet PDF文件第15页浏览型号74AUP1G132GM的Datasheet PDF文件第16页浏览型号74AUP1G132GM的Datasheet PDF文件第17页浏览型号74AUP1G132GM的Datasheet PDF文件第18页 
Nexperia  
74AUP1G132  
Low-power 2-input NAND Schmitt trigger  
Contents  
1. General description......................................................1  
2. Features and benefits.................................................. 1  
3. Applications.................................................................. 1  
4. Ordering information....................................................2  
5. Marking..........................................................................2  
6. Functional diagram.......................................................2  
7. Pinning information......................................................3  
7.1. Pinning.........................................................................3  
7.2. Pin description.............................................................3  
8. Functional description................................................. 4  
9. Limiting values............................................................. 4  
10. Recommended operating conditions........................4  
11. Static characteristics..................................................5  
11.1. Transfer characteristics..............................................7  
11.2. Waveforms transfer characteristics............................7  
12. Dynamic characteristics............................................ 8  
12.1. Waveforms and test circuit........................................ 9  
13. Application information........................................... 11  
14. Package outline........................................................ 12  
15. Abbreviations............................................................17  
16. Revision history........................................................17  
17. Legal information......................................................18  
© Nexperia B.V. 2023. All rights reserved  
For more information, please visit: http://www.nexperia.com  
For sales office addresses, please send an email to: salesaddresses@nexperia.com  
Date of release: 11 July 2023  
©
74AUP1G132  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2023. All rights reserved  
Product data sheet  
Rev. 9.1 — 11 July 2023  
19 / 19  

与74AUP1G132GM相关器件

型号 品牌 描述 获取价格 数据表
74AUP1G132GM,115 NXP 74AUP1G132 - Low-power 2-input NAND Schmitt trigger SON 6-Pin

获取价格

74AUP1G132GM,132 NXP 74AUP1G132 - Low-power 2-input NAND Schmitt trigger SON 6-Pin

获取价格

74AUP1G132GM-H NXP 暂无描述

获取价格

74AUP1G132GN NXP AUP/ULP/V SERIES, 2-INPUT NAND GATE, PDSO6, 0.90 X 1 MM, 0.35 MM HEIGHT, SOT-1115, SON-6

获取价格

74AUP1G132GN NEXPERIA Low-power 2-input NAND Schmitt triggerProduction

获取价格

74AUP1G132GS NXP AUP/ULP/V SERIES, 2-INPUT NAND GATE, PDSO6, 1 X 1 MM, 0.35 MM HEIGHT, SOT-1202, SON-6

获取价格