Datasheet > 74AUP1G09GM,132

74AUP1G09GM,132

更新时间： 2024-01-17 19:42:43

品牌	Logo	应用领域
恩智浦 - NXP		栅光电二极管逻辑集成电路触发器
页数	文件大小	规格书
19页	335K
描述
74AUP1G09 - Low-power 2-input AND gate with open-drain SON 6-Pin

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74AUP1G09GM,132 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	SON	包装说明：	VSON,
针数：	6	Reach Compliance Code：	compliant
风险等级：	1.6	Samacsys Description：	74AUP1G09 - Low-power 2-input AND gate with open-drain@en-us
系列：	AUP/ULP/V	JESD-30 代码：	R-PDSO-N6
JESD-609代码：	e3	长度：	1.45 mm
逻辑集成电路类型：	AND GATE	湿度敏感等级：	1
功能数量：	1	输入次数：	2
端子数量：	6	最高工作温度：	125 °C
最低工作温度：	-40 °C	输出特性：	OPEN-DRAIN
封装主体材料：	PLASTIC/EPOXY	封装代码：	VSON
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, VERY THIN PROFILE
传播延迟（tpd）：	24 ns	座面最大高度：	0.5 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	0.8 V
标称供电电压 (Vsup)：	1.1 V	表面贴装：	YES
技术：	CMOS	温度等级：	AUTOMOTIVE
端子面层：	Tin (Sn)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	DUAL
宽度：	1 mm

74AUP1G09GM,132 数据手册

74AUP1G09

Low-power 2-input AND gate with open-drain

Rev. 4 — 28 June 2012

Product data sheet

1. General description

The 74AUP1G09 provides the single 2-input AND gate with an open-drain output. The

output of the device is an open-drain and can be connected to other open-drain outputs to

implement active-LOW wired-OR or active-HIGH wired-AND functions.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V_CCrange from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

V_CCrange from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

2. Features and benefits

 Wide supply voltage range from 0.8 V to 3.6 V

 High noise immunity

 Complies with JEDEC standards:

 JESD8-12 (0.8 V to 1.3 V)

 JESD8-11 (0.9 V to 1.65 V)

 JESD8-7 (1.2 V to 1.95 V)

 JESD8-5 (1.8 V to 2.7 V)

 JESD8-B (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F Class 3A exceeds 5000 V

 MM JESD22-A115-A exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Low static power consumption; I_CC= 0.9 μA (maximum)

 Latch-up performance exceeds 100 mA per JESD 78 Class II

 Inputs accept voltages up to 3.6 V

 Low noise overshoot and undershoot < 10 % of V_CC

 I_OFFcircuitry provides partial Power-down mode operation

 Multiple package options

 Specified from −40 °C to +85 °C and −40 °C to +125 °C

12 3 4 5 6 7...19

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