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74AUP1G09GW-Q100 PDF预览

74AUP1G09GW-Q100

更新时间: 2024-01-30 02:02:04
品牌 Logo 应用领域
安世 - NEXPERIA 逻辑集成电路
页数 文件大小 规格书
12页 211K
描述
Low-power 2-input AND gate with open-drainProduction

74AUP1G09GW-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:unknown风险等级:5.59
JESD-609代码:e3逻辑集成电路类型:AND GATE
湿度敏感等级:1端子面层:Tin (Sn)
Base Number Matches:1

74AUP1G09GW-Q100 数据手册

 浏览型号74AUP1G09GW-Q100的Datasheet PDF文件第2页浏览型号74AUP1G09GW-Q100的Datasheet PDF文件第3页浏览型号74AUP1G09GW-Q100的Datasheet PDF文件第4页浏览型号74AUP1G09GW-Q100的Datasheet PDF文件第5页浏览型号74AUP1G09GW-Q100的Datasheet PDF文件第6页浏览型号74AUP1G09GW-Q100的Datasheet PDF文件第7页 
74AUP1G09-Q100  
Low-power 2-input AND gate with open-drain  
Rev. 4.1 — 11 July 2023  
Product data sheet  
1. General description  
The 74AUP1G09-Q100 is a single 2-input AND gate with open-drain output. Schmitt-trigger action  
at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very  
low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This  
device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables  
the output, preventing the potentially damaging backflow current through the device when it is  
powered down.  
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100  
(Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
Wide supply voltage range from 0.8 V to 3.6 V  
CMOS low power dissipation  
High noise immunity  
Overvoltage tolerant inputs to 3.6 V  
Low static power consumption; ICC = 0.9 μA (maximum)  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial Power-down mode operation  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
ESD protection:  
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V  
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74AUP1G09GW-Q100  
-40 °C to +125 °C  
TSSOP5  
plastic thin shrink small outline package; 5 leads; SOT353-1  
body width 1.25 mm  
 
 
 

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