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74ALVC162835 PDF预览

74ALVC162835

更新时间: 2024-11-17 22:56:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器
页数 文件大小 规格书
7页 92K
描述
Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26з Series Resistors in Outputs

74ALVC162835 数据手册

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September 2001  
Revised February 2002  
74ALVC162835  
Low Voltage 18-Bit Universal Bus Driver  
with 3.6V Tolerant Inputs/Outputs  
and 26Series Resistors in Outputs  
General Description  
The ALVC162835 low voltage 18-bit universal bus driver  
combines D-type latches and D-type flip-flops to allow data  
flow in transparent, latched and clocked modes.  
Features  
Compatible with PC100 DIMM module specifications  
1.65V to 3.6V VCC specifications provided  
3.6V tolerant inputs and outputs  
26series resistors in outputs  
tPD (CLK to On)  
Data flow is controlled by output-enable (OE), latch-enable  
(LE), and clock (CLK) inputs. The device operates in  
Transparent Mode when LE is held HIGH. The device  
operates in clocked mode when LE is LOW and CLK is tog-  
gled. Data transfers from the Inputs (In) to Outputs (On) on  
5.4 ns max for 3.0V to 3.6V VCC  
6.3 ns max for 2.3V to 2.7V VCC  
9.2 ns max for 1.65V to 1.95V VCC  
a Positive Edge Transition of the Clock. When OE is LOW,  
the output data is enabled. When OE is HIGH the output  
port is in a high impedance state.  
Power-off high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
Latchup conforms to JEDEC JED78  
ESD performance:  
The ALVC162835 is designed with 26series resistors in  
the outputs. This design reduces noise in applications such  
as memory address drivers, clock drivers, and bus trans-  
ceivers/transmitters.  
Human body model > 2000V  
The 74ALVC162835 is designed for low voltage (1.65V to  
3.6V) VCC applications with I/O capability up to 3.6V.  
Machine model >200V  
Note 1: To ensure the high impedance state during power up or power  
down, OE should be tied to VCC through a pulldown resistor; the minimum  
The 74ALVC162835 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
value of the resistor is determined by the current sourcing capability of the  
driver.  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74ALVC162835T  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2002 Fairchild Semiconductor Corporation  
DS500646  
www.fairchildsemi.com  

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