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74ALVC162838T

更新时间： 2024-11-17 22:56:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
6页 90K
描述
Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs/Outputs and 26з Series Resistors in the Outputs

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74ALVC162838T 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：6.10 MM, MO-153, TSSOP-48
针数：48Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.68
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G48
JESD-609代码：e0长度：12.5 mm
逻辑集成电路类型：BUS DRIVER位数：16
功能数量：1端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
传播延迟（tpd）：9.8 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.1 mm
Base Number Matches：1

74ALVC162838T 数据手册

 浏览型号74ALVC162838T的Datasheet PDF文件第2页浏览型号74ALVC162838T的Datasheet PDF文件第3页浏览型号74ALVC162838T的Datasheet PDF文件第4页浏览型号74ALVC162838T的Datasheet PDF文件第5页浏览型号74ALVC162838T的Datasheet PDF文件第6页 
November 2001  
Revised November 2001  
74ALVC162838  
Low Voltage 16-Bit Selectable Register/Buffer  
with 3.6V Tolerant Inputs/Outputs  
and 26Ω Series Resistors in the Outputs  
General Description  
Features  
■ Compatible with PC100 and PC133 DIMM module  
The ALVC162838 contains sixteen non-inverting selectable  
buffered or registered paths. The device can be configured  
to operate in a registered, or flow through buffer mode by  
utilizing the register enable (REGE) and Clock (CLK) sig-  
nals. The device operates in a 16-bit word wide mode. All  
outputs can be placed into 3-State through the use of the  
OE pin. These devices are ideally suited for buffered or  
registered 168 pin and 200 pin SDRAM DIMM memory  
modules.  
specifications  
■ 1.65V–3.6V VCC supply operation  
■ 3.6V tolerant inputs and outputs  
■ 26Ω series resistors in the outputs  
■ tPD (CLK to On)  
4.4 ns max for 3.0V to 3.6V VCC  
5.9 ns max for 2.3V to 2.7V VCC  
9.8 ns max for 1.65V to 1.95V VCC  
The 74ALVC162838 is designed for low voltage (1.65V to  
3.6V) VCC applications with I/O compatibility up to 3.6V.  
The ALVC162838 is also designed with 26Ω series resis-  
tors in the outputs. This design reduces line noise in appli-  
cations such as memory address drivers, clock drivers, and  
bus transceivers/transmitters.  
■ Power-off high impedance inputs and outputs  
■ Supports live insertion and withdrawal (Note 1)  
■ Uses patented noise/EMI reduction circuitry  
■ Latchup conforms to JEDEC JED78  
■ ESD performance:  
The 74ALVC162838 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to VCC through a pull-up resistor. The minimum  
value of the resistor is determined by the current -sourcing capability of the  
driver.  
Ordering Code:  
Ordering Code  
Package Number  
Package Descriptions  
74ALVC162838T  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
OE  
I0–I15  
O0–O15  
CLK  
Output Enable Input (Active LOW)  
Inputs  
Outputs  
Clock Input  
REGE  
Register Enable Input  
© 2001 Fairchild Semiconductor Corporation  
DS500711  
www.fairchildsemi.com  
123456

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74ALVC162838T 替代型号

型号 品牌 替代类型 描述 数据表
74VCX16838MTDX FAIRCHILD

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 Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs
74VCX16838MTD FAIRCHILD

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 Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs

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