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74ALS244

更新时间: 2024-11-03 22:53:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器
页数 文件大小 规格书
6页 76K
描述
Octal 3-STATE Bus Driver

74ALS244 数据手册

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September 1986  
Revised February 2000  
DM74ALS244A  
Octal 3-STATE Bus Driver  
General Description  
Features  
This octal 3-STATE bus driver is designed to provide the  
designer with flexibility in implementing a bus interface with  
memory, microprocessor, or communication systems. This  
device offers 64-extended temperature Grade product  
guaranteeing performance from 40°C to +85°C. The out-  
put 3-STATE gating control is organized into two separate  
groups of four buffers, and both control inputs enable the  
respective outputs when set logic LOW. The 3-STATE cir-  
cuitry contains a feature that maintains the buffer outputs in  
3-STATE (high impedance state) during power supply  
ramp-up or ramp-down. This eliminates bus glitching prob-  
lems that arise during power-up and power-down.  
Advanced low power oxide-isolated ion-implanted  
Schottky TTL process  
Functional and pin compatible with the 74LS counterpart  
Improved switching performance with less power dissi-  
pation compared with the 74LS counterpart  
Switching response specified into 500and 50 pF load  
Switching response specifications guaranteed over full  
temperature and VCC supply range  
PNP input design reduces input loading  
Ordering Code:  
Order Number  
DM74ALS244AWM  
DM74ALS244ASJ  
DM74ALS244AMSA  
DM74ALS244AN  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
M20D  
MSA20  
N20A  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Logic Diagram  
Function Table  
Input  
Output  
G
L
A
L
Y
L
L
H
X
H
Z
H
H = HIGH Level Logic State  
L = LOW Level Logic State  
X = Don't Care (Either LOW or HIGH Level Logic State)  
Z = High Impedance (OFF) State  
© 2000 Fairchild Semiconductor Corporation  
DS006212  
www.fairchildsemi.com  

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