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74ALS245 PDF预览

74ALS245

更新时间: 2024-11-03 22:53:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线收发器
页数 文件大小 规格书
6页 76K
描述
Octal 3-STATE Bus Transceiver

74ALS245 数据手册

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September 1986  
Revised February 2000  
DM74ALS245A  
Octal 3-STATE Bus Transceiver  
General Description  
Features  
This advanced low power Schottky device contains 8 pairs  
of 3-STATE logic elements configured as octal bus trans-  
ceivers. These circuits are designed for use in memory,  
microprocessor systems and in asynchronous bidirectional  
data buses. Two way communication between buses is  
controlled by the (DIR) input. Data transmits either from the  
A bus to the B bus or from the B bus to the A bus. Both the  
driver and receiver outputs can be disabled via the (G)  
enable input which causes outputs to enter the high imped-  
ance mode so that the buses are effectively isolated.  
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
Non-inverting logic output  
Glitch free bus during power up and down  
3-STATE outputs independently controlled on A and B  
buses  
Low output impedance to drive terminated transmission  
lines to 133Ω  
Switching response specified into 500/50 pF  
Specified to interface with CMOS at VOH = VCC 2V  
PNP inputs to reduce input loading  
Switching specifications guaranteed over full tempera-  
ture and VCC range  
Ordering Code:  
Order Number  
DM74ALS245AWM  
DM74ALS245ASJ  
DM74ALS245AMSA  
DM74ALS245AN  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
M20D  
MSA20  
N20A  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Control  
Inputs  
Operation  
G
L
DIR  
L
H
X
B Data to A Bus  
A Data to B Bus  
Hi-Z  
L
H
H = HIGH Logic Level  
L = LOW Logic Level  
X = Either HIGH or LOW Logic Level  
© 2000 Fairchild Semiconductor Corporation  
DS006213  
www.fairchildsemi.com  

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