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74AHCT573D,112 PDF预览

74AHCT573D,112

更新时间: 2024-11-23 15:26:35
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
19页 136K
描述
74AHC(T)573 - Octal D-type transparant latch; 3-state SOP 20-Pin

74AHCT573D,112 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SOP包装说明:7.50 MM, PLASTIC, MO-013, SOT163-1, SOP-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.3
系列:AHCT/VHCT/VTJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:9.5 ns
传播延迟(tpd):11 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

74AHCT573D,112 数据手册

 浏览型号74AHCT573D,112的Datasheet PDF文件第2页浏览型号74AHCT573D,112的Datasheet PDF文件第3页浏览型号74AHCT573D,112的Datasheet PDF文件第4页浏览型号74AHCT573D,112的Datasheet PDF文件第5页浏览型号74AHCT573D,112的Datasheet PDF文件第6页浏览型号74AHCT573D,112的Datasheet PDF文件第7页 
74AHC573; 74AHCT573  
Octal D-type transparant latch; 3-state  
Rev. 7 — 8 November 2011  
Product data sheet  
1. General description  
The 74AHC573; 74AHCT573 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard  
No. 7A.  
The 74AHC573; 74AHCT573 consists of eight D-type transparent latches featuring  
separate D-type inputs for each latch and 3-state true outputs for bus oriented  
applications. A latch enable input (LE) and an output enable input (OE) are common to all  
latches.  
When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the  
latches are transparent, i.e. a latch output will change state each time its corresponding  
Dn input changes. When pin LE is LOW, the latches store the information that is present  
at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE.  
When pin OE is LOW, the contents of the 8 latches are available at the outputs. When  
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE  
input does not affect the state of the latches.  
The 74AHC573; 74AHCT573 is functionally identical to the 74AHC373; 74AHCT373, but  
has a different pin arrangement.  
2. Features and benefits  
Balanced propagation delays  
All inputs have a Schmitt trigger action  
Common 3-state output enable input  
Functionally identical to the 74AHC373; 74AHCT373  
Inputs accept voltages higher than VCC  
Input levels:  
For 74AHC573: CMOS input level  
For 74AHCT573: TTL input level  
ESD protection:  
HBM EIA/JESD22-A114E exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V  
CDM EIA/JESD22-C101C exceeds 1000 V  
Multiple package options  
Specified from 40 C to +85 C and from 40 C to +125 C  
 
 

74AHCT573D,112 替代型号

型号 品牌 替代类型 描述 数据表
74AHCT573D,118 NXP

完全替代

74AHC(T)573 - Octal D-type transparant latch; 3-state SOP 20-Pin
74AHCT573D-T NXP

类似代替

IC AHCT/VHCT/VT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MO-013, SOT16
SN74AHCT573DW TI

功能相似

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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