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74AHCT574BQ PDF预览

74AHCT574BQ

更新时间: 2024-11-19 04:47:35
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
18页 107K
描述
Octal D-type flip-flop; positive edge-trigger; 3-state

74AHCT574BQ 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否无铅: 不含铅
是否Rohs认证: 符合生命周期:Transferred
零件包装代码:QFN包装说明:HVQCCN, LCC20,.1X.18,20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.44
系列:AHCT/VHCT/VTJESD-30 代码:R-XQCC-N20
JESD-609代码:e4长度:4.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:75000000 Hz最大I(ol):0.008 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC20,.1X.18,20
封装形状:RECTANGULAR封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 V传播延迟(tpd):13.5 ns
认证状态:Not Qualified座面最大高度:1 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:2.5 mm
Base Number Matches:1

74AHCT574BQ 数据手册

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74AHC574; 74AHCT574  
Octal D-type flip-flop; positive edge-trigger; 3-state  
Rev. 02 — 24 January 2008  
Product data sheet  
1. General description  
The 74AHC574; 74AHCT574 are high-speed Si-gate CMOS devices and are pin  
compatible with Low Power Schottky TTL (LSTTL). They are specified in compliance with  
JEDEC standard no. 7A.  
The 74AHC574; 74AHCT574 are octal D-type flip-flops featuring separate D-type inputs  
for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an  
output enable (OE) input are common to all flip-flops.  
The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold  
times requirements on the LOW-to-HIGH CP transition.  
When OE is LOW the contents of the 8 flip-flops are available at the outputs. When OE is  
HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does  
not affect the state of the flip-flops.  
The 74AHC574; 74AHCT574 is functionally identical to the 74AHC564; 74AHCT564, but  
has non-inverting outputs. The 74AHC574; 74AHCT574 is functionally identical to  
the 74AHC374; 74AHCT374, but has a different pinning.  
2. Features  
I Balanced propagation delays  
I All inputs have a Schmitt-trigger action  
I 3-state non-inverting outputs for bus orientated applications  
I 8-bit positive, edge-triggered register  
I Independent register and 3-state buffer operation  
I Common 3-state output enable input  
I For 74AHC574 only: operates with CMOS input levels  
I For 74AHCT574 only: operates with TTL input levels  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
N CDM JESD22-C101C exceeds 1000 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  

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