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74AHCT240BQ,115 PDF预览

74AHCT240BQ,115

更新时间: 2024-10-28 14:50:51
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恩智浦 - NXP 驱动逻辑集成电路
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74AHCT240BQ,115 数据手册

 浏览型号74AHCT240BQ,115的Datasheet PDF文件第1页浏览型号74AHCT240BQ,115的Datasheet PDF文件第3页浏览型号74AHCT240BQ,115的Datasheet PDF文件第4页浏览型号74AHCT240BQ,115的Datasheet PDF文件第5页浏览型号74AHCT240BQ,115的Datasheet PDF文件第6页浏览型号74AHCT240BQ,115的Datasheet PDF文件第7页 
NXP Semiconductors  
74AHC240; 74AHCT240  
Octal buffer/line driver; inverting; 3-state  
4. Functional diagram  
1
EN  
18  
2
16  
14  
12  
4
6
8
2
1Y0 18  
2Y0  
1A0  
3
17 2A0  
4
1A1  
2A1  
1Y1 16  
15  
5
2Y1  
19  
11  
EN  
6
14  
7
1Y2  
2Y2  
1A2  
2A2  
13  
9
8
12  
9
1Y3  
2Y3  
1A3  
2A3  
13  
15  
17  
7
5
3
11  
1OE  
2OE  
1
19  
mgu779  
mgu778  
Fig 1. Logic symbol  
Fig 2. IEC logic symbol  
5. Pinning information  
5.1 Pinning  
74AHC240  
74AHCT240  
terminal 1  
index area  
74AHC240  
74AHCT240  
2
3
4
5
6
7
8
9
19  
1A0  
2OE  
1Y0  
2A0  
1Y1  
2A1  
1Y2  
2A2  
1Y3  
18  
17  
16  
15  
14  
13  
12  
2Y0  
1A1  
2Y1  
1A2  
2Y2  
1A3  
2Y3  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1OE  
1A0  
2Y0  
1A1  
2Y1  
1A2  
2Y2  
1A3  
2Y3  
GND  
V
CC  
2OE  
1Y0  
2A0  
1Y1  
2A1  
1Y2  
2A2  
1Y3  
2A3  
3
4
5
6
(1)  
GND  
7
8
9
001aal193  
10  
Transparent top view  
001aal192  
(1) This is not a supply pin. The substrate is attached to this  
pad using conductive die attach material. There is no  
electrical or mechanical requirement to solder this pad.  
However, if it is soldered, the solder land should remain  
floating or be connected to GND.  
Fig 3. Pin configuration SO20 and TSSOP20  
Fig 4. Pin configuration DHVQFN20  
74AHC_AHCT240  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 4 — 25 September 2013  
2 of 16  
 
 
 

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