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74AHCT157BQ,115 PDF预览

74AHCT157BQ,115

更新时间: 2024-11-30 20:51:35
品牌 Logo 应用领域
恩智浦 - NXP PC逻辑集成电路
页数 文件大小 规格书
16页 86K
描述
74AHC(T)157 - Quad 2-input multiplexer QFN 16-Pin

74AHCT157BQ,115 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:QFN包装说明:2.50 X 3.50 MM, 0.85 MM HEIGHT, MO-241, SOT763-1, DHVQFN-16
针数:16Reach Compliance Code:compliant
风险等级:8.57Base Number Matches:1

74AHCT157BQ,115 数据手册

 浏览型号74AHCT157BQ,115的Datasheet PDF文件第2页浏览型号74AHCT157BQ,115的Datasheet PDF文件第3页浏览型号74AHCT157BQ,115的Datasheet PDF文件第4页浏览型号74AHCT157BQ,115的Datasheet PDF文件第5页浏览型号74AHCT157BQ,115的Datasheet PDF文件第6页浏览型号74AHCT157BQ,115的Datasheet PDF文件第7页 
74AHC157; 74AHCT157  
Quad 2-input multiplexer  
Rev. 02 — 9 November 2007  
Product data sheet  
1. General description  
The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with  
Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC  
standard no. 7A.  
The 74AHC/AHCT157 are quad 2-input multiplexer which select 4 bits of data from two  
sources under the control of a common data select input (S). The enable input (E) is  
active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of  
all other input conditions.  
Moving the data from two groups of registers to four common output buses is a common  
use of the 74AHC/AHCT157. The state of the common data select input (S) determines  
the particular register from which the data comes. It can also be used as function  
generator. The device is useful for implementing highly irregular logic by generating any  
four of the 16 different functions of two variables with one variable common. The  
74AHC/AHCT157 is logic implementation of a 4-pole, 2-position switch, where the  
position of the switch is determine by the logic levels applied to S.  
The logic equations are:  
1Y = E × (1I1 × S + 1I0 × S)  
2Y = E × (2I1 × S + 2I0 × S)  
3Y = E × (3I1 × S + 3I0 × S)  
4Y = E × (4I1 × S + 4I0 × S)  
The 74AHC/AHCT157 is identical to the 74AHC/AHCT158 but has non-inverting (true)  
outputs.  
2. Features  
Balanced propagation delays  
All inputs have a Schmitt-trigger action  
Inputs accepts voltages higher than VCC  
Multiple input enable for easy expansion  
Ideal for memory chip select decoding  
For 74AHC157 only: operates with CMOS input levels  
For 74AHCT157 only: operates with TTL input levels  
ESD protection:  
HBM JESD22-A114E exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101C exceeds 1000 V  
 
 

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