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74AHCT157PW PDF预览

74AHCT157PW

更新时间: 2024-11-19 11:12:15
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
15页 260K
描述
Quad 2-input multiplexerProduction

74AHCT157PW 技术参数

是否Rohs认证:符合生命周期:Active
包装说明:TSSOP-16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.05
Is Samacsys:N系列:AHCT/VHCT/VT
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:5 mm逻辑集成电路类型:MULTIPLEXER
湿度敏感等级:1功能数量:4
输入次数:2输出次数:1
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):13 ns
认证状态:Not Qualified座面最大高度:1.1 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

74AHCT157PW 数据手册

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74AHC157; 74AHCT157  
Quad 2-input multiplexer  
Rev. 3 — 10 September 2020  
Product data sheet  
1. General description  
The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with Low  
Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.  
The 74AHC/AHCT157 are quad 2-input multiplexer which select 4 bits of data from two sources  
under the control of a common data select input (S). The enable input (E) is active LOW. When E is  
HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions.  
Moving the data from two groups of registers to four common output buses is a common use of  
the 74AHC/AHCT157. The state of the common data select input (S) determines the particular  
register from which the data comes. It can also be used as function generator. The device is useful  
for implementing highly irregular logic by generating any four of the 16 different functions of two  
variables with one variable common. The 74AHC/AHCT157 is logic implementation of a 4-pole,  
2-position switch, where the position of the switch is determine by the logic levels applied to S.  
The logic equations are:  
1Y = E × (1I1 × S + 1I0 × S)  
2Y = E × (2I1 × S + 2I0 × S)  
3Y = E × (3I1 × S + 3I0 × S)  
4Y = E × (4I1 × S + 4I0 × S)  
2. Features  
Balanced propagation delays  
All inputs have a Schmitt-trigger action  
Inputs accepts voltages higher than VCC  
Multiple input enable for easy expansion  
Ideal for memory chip select decoding  
For 74AHC157 only: operates with CMOS input levels  
For 74AHCT157 only: operates with TTL input levels  
ESD protection:  
HBM JESD22-A114E exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101C exceeds 1000 V  
Multiple package options  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
 
 

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