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74AHC573BQ PDF预览

74AHC573BQ

更新时间: 2023-09-03 20:27:42
品牌 Logo 应用领域
安世 - NEXPERIA 驱动逻辑集成电路
页数 文件大小 规格书
16页 276K
描述
Octal D-type transparent latch; 3-stateProduction

74AHC573BQ 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:HVQCCN,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.28
Is Samacsys:N系列:AHC/VHC/H/U/V
JESD-30 代码:R-PQCC-N20JESD-609代码:e4
长度:4.5 mm逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装形状:RECTANGULAR
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):19.5 ns座面最大高度:1 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:2.5 mm
Base Number Matches:1

74AHC573BQ 数据手册

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74AHC573; 74AHCT573  
Octal D-type transparent latch; 3-state  
Rev. 8 — 13 July 2020  
Product data sheet  
1. General description  
The 74AHC573; 74AHCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device  
features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs  
enter the latches. In this condition the latches are transparent, a latch output will change each time  
its corresponding D-input changes. When LE is LOW the latches store the information that was  
present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE  
causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not  
affect the state of the latches. Inputs are overvoltage tolerant. This feature allows the use of these  
devices as translators in mixed voltage environments.  
2. Features and benefits  
Wide supply voltage range from 2.0 V to 5.5 V  
Balanced propagation delays  
All inputs have Schmitt-trigger action  
Overvoltage tolerant inputs to 5.5 V  
High noise immunity  
CMOS low power dissipation  
Common 3-state output enable input  
Functionally identical to the 74AHC373; 74AHCT373  
Input levels:  
For 74AHC573: CMOS input level  
For 74AHCT573: TTL input level  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level A  
Multiple package options  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
 
 

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