Datasheet > 74AHC573BQ-Q100

74AHC573BQ-Q100

更新时间： 2024-02-25 11:39:59

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
19页	732K
描述
Octal D-type transparant latch 3-state

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74AHC573BQ-Q100 数据手册

74AHC573-Q100; 74AHCT573-Q100

Octal D-type transparant latch; 3-state

Rev. 1 — 10 June 2013

Product data sheet

1. General description

The 74AHC573-Q100; 74AHCT573-Q100 is a high-speed Si-gate CMOS device and is

pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with

JEDEC standard No. 7A.

The 74AHC573-Q100; 74AHCT573-Q100 consists of eight D-type transparent latches

featuring separate D-type inputs for each latch and 3-state true outputs for bus oriented

applications. A latch enable input (LE) and an output enable input (OE) are common to all

latches.

When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the

latches are transparent, i.e. a latch output will change state each time its corresponding

Dn input changes. When pin LE is LOW, the latches store the information that is present

at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE.

When pin OE is LOW, the contents of the 8 latches are available at the outputs. When

pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE

input does not affect the state of the latches.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Balanced propagation delays

 All inputs have a Schmitt trigger action

 Common 3-state output enable input

 Inputs accept voltages higher than V_CC

 Input levels:

 For 74AHC573-Q100: CMOS input level

 For 74AHCT573-Q100: TTL input level

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 Multiple package options

12 3 4 5 6 7...19

中文翻译

下载PDF

与74AHC573BQ-Q100相关器件

型号	品牌	获取价格	描述	数据表
74AHC573BQ-Q100X	NXP	获取价格	74AHC(T)573-Q100 - Octal D-type transparant latch; 3-state QFN 20-Pin
74AHC573D	NXP	获取价格	Octal D-type transparent latch; 3-state
74AHC573D	NEXPERIA	获取价格	Octal D-type transparent latch; 3-stateProduction
74AHC573D/T3	NXP	获取价格	IC AHC/VHC/H/U/V SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MS-013, SOT-
74AHC573D-Q100	NEXPERIA	获取价格	Octal D-type transparant latch 3-state
74AHC573D-T	NXP	获取价格	IC AHC/VHC/H/U/V SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 7.50 MM, PLASTIC, MO-013, SOT1
74AHC573PW	NXP	获取价格	Octal D-type transparent latch; 3-state
74AHC573PW	NEXPERIA	获取价格	Octal D-type transparent latch; 3-stateProduction
74AHC573PW,112	NXP	获取价格	74AHC(T)573 - Octal D-type transparant latch; 3-state TSSOP2 20-Pin
74AHC573PW,118	NXP	获取价格	74AHC(T)573 - Octal D-type transparant latch; 3-state TSSOP2 20-Pin