Datasheet > 74AHC377_08

74AHC377_08

更新时间： 2024-09-24 11:48:07

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
16页	94K
描述
Octal D-type flip-flop with data enable; positive-edge trigger

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74AHC377_08 数据手册

74AHC377; 74AHCT377

Octal D-type ﬂip-ﬂop with data enable; positive-edge trigger

Rev. 02 — 12 June 2008

Product data sheet

1. General description

The 74AHC377; 74AHCT377 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). It is speciﬁed in compliance with JEDEC standard

No. 7-A.

The 74AHC377; 74AHCT377 has eight edge-triggered, D-type ﬂip-ﬂops with individual D

inputs and Q outputs. A common clock input (CP) loads all ﬂip-ﬂops simultaneously when

the data enable input (E) is LOW. The state of each D input, one set-up time before the

LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the

ﬂip-ﬂop. The E input is only required to be stable one set-up time prior to the

LOW-to-HIGH transition for predictable operation.

For versions associated with the 74AHC377; 74AHCT377, refer to the following:

• For the master reset version, see 74AHC273; 74AHCT273

• For the transparent latch version, see 74AHC373; 74AHCT373

• For the 3-state version, see 74AHC374; 74AHCT374

2. Features

I Balanced propagation delays

I All inputs have Schmitt-trigger actions

I Inputs accept voltages higher than V_CC

I Ideal for addressable register applications

I Data enable for address and data synchronization

I Eight positive-edge triggered D-type ﬂip-ﬂops

I Input levels:

N For 74AHC377: CMOS level

N For 74AHCT377: TTL level

I ESD protection:

N HBM EIA/JESD22-A114E exceeds 2000 V

N MM EIA/JESD22-A115-A exceeds 200 V

N CDM EIA/JESD22-C101C exceeds 1000 V

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

12 3 4 5 6 7...16

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型号	品牌	获取价格	描述	数据表
74AHC377D	NXP	获取价格	Octal D-type flip-flop with data enable; positive-edge trigger
74AHC377D,112	NXP	获取价格	74AHC(T)377 - Octal D-type flip-flop with data enable; positive-edge trigger SOP 20-Pin
74AHC377D,118	NXP	获取价格	74AHC(T)377 - Octal D-type flip-flop with data enable; positive-edge trigger SOP 20-Pin
74AHC377D-Q100	NXP	获取价格	IC D FLIP-FLOP, FF/Latch
74AHC377D-Q100	NEXPERIA	获取价格	Octal D-type flip-flop with data enable; positive-edge trigger
74AHC377PW	NXP	获取价格	Octal D-type flip-flop with data enable; positive-edge trigger
74AHC377PW,118	NXP	获取价格	74AHC(T)377 - Octal D-type flip-flop with data enable; positive-edge trigger TSSOP2 20-Pin
74AHC377PW-Q100	NXP	获取价格	IC D FLIP-FLOP, FF/Latch
74AHC377PW-Q100	NEXPERIA	获取价格	Octal D-type flip-flop with data enable; positive-edge trigger
74AHC377PW-Q100J	NXP	获取价格	74AHC(T)377-Q100 - Octal D-type flip-flop with data enable; positive-edge trigger TSSOP2 2