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74ACT825SCQR PDF预览

74ACT825SCQR

更新时间: 2024-11-02 20:21:39
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
8页 167K
描述
ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, SOIC-24

74ACT825SCQR 技术参数

生命周期:Obsolete包装说明:SOP,
Reach Compliance Code:unknown风险等级:5.71
Is Samacsys:N其他特性:WITH DUAL OUTPUT ENABLE
系列:ACTJESD-30 代码:R-PDSO-G24
长度:15.4 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):10.5 ns
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

74ACT825SCQR 数据手册

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March 1993  
54ACT/74ACT825  
8-Bit D Flip-Flop  
General Description  
Features  
Y
Outputs source/sink 24 mA  
The ’ACT825 is an 8-bit buffered register. They have Clock  
Enable and Clear features which are ideal for parity bus  
interfacing in high performance microprogramming systems.  
Also included are multiple enables that allow multi-use con-  
trol of the interface. The ’ACT825 has noninverting outputs  
and is fully compatible with AMD’s Am29825.  
Y
Inputs and outputs are on opposite sides  
Y
’ACT825 has TTL-compatible inputs  
Y
Standard Military Drawing (SMD)  
Ð ’ACT825: 5962-91611  
Logic Symbols  
Connection Diagrams  
Pin Assignment  
for DIP, Flatpak and SOIC  
IEEE/IEC  
TL/F/9895–1  
TL/F/9895–2  
TL/F/9895–3  
Pin Assignment  
for LCC  
Pin Names  
D D  
Description  
Data Inputs  
Data Outputs  
Output Enables  
Clock Enable  
Clear  
0
O O  
7
0
7
OE , OE , OE  
3
1
2
EN  
CLR  
CP  
Clock Input  
TL/F/9895–4  
FACTTM is a trademark of National Semiconductor.  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9895  
RRD-B30M75/Printed in U. S. A.  

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