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74ACT323LCT PDF预览

74ACT323LCT

更新时间: 2024-11-01 13:04:51
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 存储
页数 文件大小 规格书
6页 57K
描述
Parallel In Parallel Out, ACT Series, 8-Bit, Bidirectional, True Output, CMOS, CQCC20, CERAMIC, LCC-20

74ACT323LCT 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCN,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.71其他特性:HOLD MODE; COMMON I/O PINS; GATED OUTPUT CONTROL
计数方向:BIDIRECTIONAL系列:ACT
JESD-30 代码:S-CQCC-N20长度:8.89 mm
逻辑集成电路类型:PARALLEL IN PARALLEL OUT位数:8
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装形状:SQUARE封装形式:CHIP CARRIER
认证状态:Not Qualified座面最大高度:2.54 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD触发器类型:POSITIVE EDGE
宽度:8.89 mm最小 fmax:125 MHz
Base Number Matches:1

74ACT323LCT 数据手册

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June 1988  
Revised October 1998  
74ACT323  
8-Bit Universal Shift/Storage Register with  
Synchronous Reset and Common I/O Pins  
General Description  
Features  
ICC and IOZ reduced by 50%  
The ACT323 is an 8-bit universal shift/storage register with  
3-STATE outputs. Parallel load inputs and flip-flop outputs  
are multiplexed to minimize pin count. Separate serial  
inputs and outputs are provided for Q0 and Q7 to allow  
Common parallel I/O for reduced pin count  
Additional serial inputs and outputs for expansion  
Four operating modes: shift left, shift right, load and  
store  
easy cascading. Four operation modes are possible: hold  
(store), shift left, shift right and parallel load.  
3-STATE outputs for bus-oriented applications  
Outputs source/sink 24 mA  
TTL-compatible inputs  
Ordering Code:  
Order Number Package Number  
Package Description  
74ACT323PC  
N20A  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
Pin Assignment  
for DIP  
Pin Descriptions  
Pin Name  
CP  
Description  
Clock Pulse Input  
DS0  
Serial Data Input for Right Shift  
Serial Data Input for Left Shift  
Mode Select Inputs  
DS7  
S0, S1  
SR  
Synchronous Reset Input  
3-STATE Output Enable Inputs  
Multiplexed Parallel Data Inputs or  
3-STATE Parallel Data Outputs  
Serial Outputs  
OE1, OE2  
I/O0–I/O7  
Q0, Q7  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS009787.prf  
www.fairchildsemi.com  

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