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74ACT18825SSCX PDF预览

74ACT18825SSCX

更新时间: 2024-11-10 23:24:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 51K
描述
9-Bit Buffer/Driver

74ACT18825SSCX 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP56,.4
针数:56Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.37
控制类型:ENABLE LOW系列:ACT
JESD-30 代码:R-PDSO-G56JESD-609代码:e3
长度:18.415 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:9功能数量:2
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP56,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:9.2 ns传播延迟(tpd):9 ns
认证状态:Not Qualified座面最大高度:2.74 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

74ACT18825SSCX 数据手册

 浏览型号74ACT18825SSCX的Datasheet PDF文件第2页浏览型号74ACT18825SSCX的Datasheet PDF文件第3页浏览型号74ACT18825SSCX的Datasheet PDF文件第4页浏览型号74ACT18825SSCX的Datasheet PDF文件第5页浏览型号74ACT18825SSCX的Datasheet PDF文件第6页 
August 1999  
Revised October 1999  
74ACT18825  
18-Bit Buffer/Line Driver with 3-STATE Outputs  
General Description  
Features  
The ACT18825 contains eighteen non-inverting buffers  
with 3-STATE outputs designed to be employed as a mem-  
ory and address driver, clock driver, or bus oriented trans-  
mitter/receiver. The device is byte controlled. Each byte  
has separate 3-STATE control inputs which can be shorted  
together for full 18-bit operation.  
Broadside pinout allows for easy board layout  
Separate control logic for each byte  
Extra data width for wider address/data paths or buses  
carrying parity  
Outputs source/sink 24 mA  
TTL-compatible inputs  
Ordering Code:  
Order Number  
74ACT18825SSC  
74ACT18825MTD  
Package Number  
MS56A  
Package Description  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD56  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
OEn  
Output Enable Input (Active LOW)  
I0–I17  
O0–O17  
Inputs  
Outputs  
FACT , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS0500292  
www.fairchildsemi.com  

74ACT18825SSCX 替代型号

型号 品牌 替代类型 描述 数据表
74ACT16823DLG4 TI

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18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
74ACT16823DL TI

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18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

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