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74ACT240M PDF预览

74ACT240M

更新时间: 2024-11-10 22:56:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
8页 81K
描述
OCTAL BUS BUFFER WITH 3 STATE OUTPUTS INVERTED

74ACT240M 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.04
Is Samacsys:N控制类型:ENABLE LOW
系列:ACTJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:5 VProp。Delay @ Nom-Sup:8.5 ns
传播延迟(tpd):8.5 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:7.5 mmBase Number Matches:1

74ACT240M 数据手册

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74ACT240  
OCTAL BUS BUFFER  
WITH 3 STATE OUTPUTS (INVERTED)  
HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V  
LOW POWER DISSIPATION:  
ICC = 8 µA (MAX.) at TA = 25 oC  
COMPATIBLE WITH TTL OUTPUTS  
V
IH = 2V (MIN), V = 0.8V (MAX)  
IL  
50TRANSMISSION LINE DRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL =24 mA (MIN)  
BALANCED PROPAGATION DELAYS:  
tPLH tPHL  
OPERATING VOLTAGE RANGE:  
B
M
(Plastic Package)  
(Micro Package)  
ORDER CODES :  
74ACT240B  
74ACT240M  
G control output governs four BUS BUFFERs.  
This device is desibned to be used with 3 state  
memory address drivers, etc.  
VCC (OPR) = 4.5V to 5.5V  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 240  
IMPROVED LATCH-UP IMMUNITY  
The device is designed to interface directly High  
Speed CMOS systems with TTL, NMOS and  
CMOS output voltage levels.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The ACT240 is an advanced CMOS OCTAL BUS  
BUFFER (3-STATE) fabricated with sub-micron  
silicon gate and double-layer metal wiring C2MOS  
technology. It is ideal for low power applications  
mantaining high speed operation similar to  
equivalentBipolar Schottky TTL.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
April 1997  

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