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74ACT11373DWE4 PDF预览

74ACT11373DWE4

更新时间: 2024-11-25 14:40:15
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
20页 916K
描述
ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SOP-24

74ACT11373DWE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP24,.4针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.51系列:ACT
JESD-30 代码:R-PDSO-G24JESD-609代码:e4
长度:15.4 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:11.8 ns传播延迟(tpd):12.2 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

74ACT11373DWE4 数据手册

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74ACT11373  
OCTAL TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SCAS015B – JUNE 1987 – REVISED APRIL 1996  
DB, DW, OR NT PACKAGE  
(TOP VIEW)  
Eight Latches in a Single Package  
3-State Bus Driving True Outputs  
Full Parallel Access for Loading  
Buffered Input and Output-Enable Pins  
Inputs Are TTL-Voltage Compatible  
1Q  
2Q  
OE  
1D  
2D  
3D  
4D  
V
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
2
3Q  
3
4Q  
4
Flow-Through Architecture Optimizes  
PCB Layout  
GND  
GND  
GND  
GND  
5Q  
5
6
CC  
Center-Pin V  
Minimize High-Speed Switching Noise  
and GND Configurations  
CC  
7
V
CC  
8
5D  
6D  
7D  
8D  
LE  
EPIC (Enhanced-Performance Implanted  
CMOS) 1- m Process  
9
10  
11  
12  
6Q  
500-mA Typical Latch-Up Immunity at  
125°C  
7Q  
8Q  
Package Options Include Plastic  
Small-Outline (DW) and Shrink  
Small-Outline (DB) Packages, and Standard  
Plastic 300-mil DIPs (NT)  
description  
This 8-bit latch features 3-state outputs designed specifically for driving highly-capacitive or relatively  
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus  
drivers, and working registers.  
The eight latches of the 74ACT11373 are transparent D-type latches. While the latch-enable (LE) input is high,  
the Q outputs follow the data (D) inputs. When the enable is taken low, the Q outputs are latched at the levels  
that were set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impendance third state and increased drive provide the capability to drive  
the bus lines in a bus-organized system without need for interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are off.  
The 74ACT11373 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
LE  
H
H
L
OE  
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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